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<lambda>
if I want to use yosys primitives from VHDL via ghdl, I have to find some way to map the mangled component names from ghdl back to the actual primitive names. until now I've just written simple verilog wrapper modules, which works great for the likes of PLLs, but I've hit a snag with OBUFDS: the top module creates OBUFs for all its outputs, and the inner (verilog) module containing the OBUFDS is
<lambda>
packed in front of them, which of course won't work: http://ix.io/2d9r
<lambda>
is there either a way to remove the OBUFs, or even better, map the mangled names to the primitives directly without a separate module (in the case of OBUFDS, the mangling is just everything being turned to lowercase)
<daveshah>
lambda: try either -flatten (to work with a flat netlist instead) or -noiopad (to disable obuf insertion)
<lambda>
daveshah: I'm already using -flatten with synth_xilinx - is nextpnr-xilinx ok with no iopads in the json?
<lambda>
also, no tristate buffers with -noiopad :/
<daveshah>
Yeah, nextpnr-xilinx prefers iopad
<daveshah>
I think the problem is attributes are being lost here
<daveshah>
Can you try read_verilog +/xilinx/cells_xtra.v _before_ any GHDL stuff?
<lambda>
daveshah: no change
<lambda>
currently trying some `select` magic to drop all OBUFs after OBUFDS
<daveshah>
Incidentally, what do you mean by "map the mangled component names"?
<daveshah>
The problem is almost certainly that the attribute telling Yosys not to insert OBUFs on OBFUDS top level pins is being lost
<lambda>
daveshah: well, ghdl(synth) converts all identifiers to lowercase, so OBUFDS(I, O, OB) becomes obufds(i, o, ob). I somehow need to get from that back to the proper primitive name, so I just create a verilog module 'obufds' that passes all its ports through to an OBUFDS component.
<daveshah>
lambda: and just to check, your Yosys is reasonably up to date?
<lambda>
daveshah: 69c2d384, latest master
<daveshah>
lambda: If you run synth_xilinx just on your obufds verilog module with no GHDL involved, do you still get spurious OBUFs?
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<lambda>
daveshah: nope, that's just IBUF + OBUFDS. doesn't seem to be exclusive the ghdl though, if I recreate the same in verilog (top verilog module includes the wrapper obufds module), I also get the extra OBUFs.
<daveshah>
I think the submodule might be confusing things
<daveshah>
If you remove that module and have read_verilog +/xilinx/cells_xtra.v before GHDL, does it fix the capitalisation issue?
<lambda>
no, then I just get an obufds blackbox in the output, I don't think ghdlsynth looks at the available components in yosys at all yet.
<lambda>
that is, IBUF + obufds + 2x OBUF, which makes sense since it can't know obufds is anything special
<lambda>
oh hey, if I flatten *before* synth_xilinx, it works! I'm guessing it's just that OBUFs are added to all the top module's outputs before flattening, where it doesn't know those outputs are connected to an OBUFDS - if I flatten first, no OBUFs are added in the first place.
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<lambda>
nevermind, that was a false flag.
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<lambda>
hrmm, `flatten` seems to add BUFs itself, can I get it to not do that?
<ZirconiumX>
It's probably doing it for things like tristate logic
<mwk>
hmm.
<mwk>
lambda: ... you know what, I'll cook a patch
<mwk>
give me an hour or so
<lambda>
mwk: awesome, thanks :)
<lambda>
mwk: I guess the "proper" thing to do would be to respect that attribute of OBUFDS even when it's somewhere deeper in the hierarchy, the manual flatten was just an attempt at a workaround
<mwk>
yes, we'd have to trace the wire from the top-level port
<mwk>
through assigns and submodule ports
<mwk>
*wires
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<mwk>
which is messy to do fully correctly, because in theory you could have "pass thru" modules that connect the top level port to a random wire in the top module, which is then buffered by *another* module, etc
<mwk>
but I think I'll just solve the simple case and call it a day
<lambda>
it's definitely an improvement already, yeah
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<tpb>
Title: iopadmap: Look harder for already-present buffers. by mwkmwkmwk · Pull Request #1731 · YosysHQ/yosys · GitHub (at github.com)
<mwk>
sorry it took so long
<lambda>
mwk: no problem at all, we all know this is way better support than most commercial tools can offer :) I'll try it in just a bit
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<lambda>
mwk: it works now! there are some BUFs left in the final output, are they just for renaming the signal? nextpnr-xilinx doesn't seem to care about them, so it's all good. http://ix.io/2dbp
<daveshah>
They aren't actually cells at all, just how `show` visualises connections. They don't end up in the JSON netlist at all (instead two netnames just point to the same net index)
<mwk>
lambda: BUFs are verilog "assign" statements, more or less
<lambda>
ah, I see
<mwk>
they... kind of don't have well-defined semantics in yosys, which annoys me greatly
<mwk>
anyway, good to know
<mwk>
I'll add some tests to this PR and get it merged
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<strubi>
daveshah, is there actually a BRAM test suite apart from tests/bram that checks against vendor primitive models, do you know?
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<ZirconiumX>
Memory is a pretty difficult thing to test as such
<strubi>
I was just trying to co-simulate against a DP16KD (ECP5) to see if I got the wiring and /CS right
<strubi>
that kinda works, but for the big picture (not breaking stuff..) I was wondering on how to proceed
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