clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<attie> lambda: EDIF isn't exactly a well-defined format. There are several known issues related to vector order. This may be helpful? https://github.com/YosysHQ/yosys/pull/1489 (the last comment links to two issues discussing the subject)
<lambda> attie: yeah, #830 seems like (one of) my issues. I'll just use verilog netlists when I need to run something through vivado in the future though
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<ZirconiumX> Does pipelining make any significant difference in a design's routability?
<ZirconiumX> My intuition says no because things have to now be routed through your pipeline stages, but maybe it's wrong
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<Sarayan> I would have said yes, it makes it easier, because there are less random dependencies?
<ZirconiumX> Well, the pipeline stages will have pretty huge fan-out in my benchmark
<Sarayan> ah
<Sarayan> well then :-)
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<ZirconiumX> Yosys' naming difficulties are rather annoying at times
<ZirconiumX> dirgolem.o_souEa$next_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O
<lambda> yeah, https://github.com/YosysHQ/yosys/pull/1730 was definitely a step in the right direction, maybe some more of those can be sprinkled around
<ZirconiumX> ABC is not helping much here :P
<ZirconiumX> FlowMap is a lot more helpful, but also explodes the design, so
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