clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<thardin> does yosys always generate long multiplication when multiplying large numbers, or does it sometimes attempt karatsuba or toom-cook multiplication?
<mwk> always long multiplication
<thardin> as suspected. I guess one could have modules for the other types and have a shell script that somehow tries various combinations and sees what nextpnr makes of each one
<thardin> ah or even just have multiple .v files each with their own implementation then just have a makefile target for each combination
<ZirconiumX> It would be possible to add support for more-efficient long multiplication, I think
<mwk> is it really more efficient for multipliers of reasonable size, though?
<thardin> "It Depends" I suspect
<thardin> software like GMP tend to switch algos depending on size. I suspect something similar could be useful here
<thardin> at the very least it would be useful if a synthesized design doesn't fit
<thardin> say if you're doing RSA on a small chip, it might be useful
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<FSM_Dude> Hey! Could someone help me with some small verilog module Im making? Trying to get a 2 state FSM in my module, but Yosys does not detect it for some reason
<mwk> that's because 2-state FSM is too boring
<mwk> it's a single ff either way
<mwk> also, uh... the yosys fsm infrastructure is not exactly great
<FSM_Dude> Oh that's a pity
<FSM_Dude> I wanted to have a two state state machine and export it to visualise it
<mwk> hmm, how do you visualize that stuff?
<mwk> well
<mwk> you could comment out the right check...
<mwk> interesting usecase btw, thank you
<mwk> for bringing it to my attention
<FSM_Dude> The reason I want a small FSM is that I try out some other state encoding techniques which I implemented.
<FSM_Dude> It's very convenient to work with a small FSM, because the changes I make are easier to follow and understand
<mwk> well, for a two-state FSM there is exactly one encoding that makes sense
<mwk> anyway
<mwk> passes/fsm/fsm_detect.cc function detect_fsm
<mwk> comment out the "if (wire->width <= 1)" near the beginning
<mwk> this should enable two-state FSMs
<FSM_Dude> Thanks Ill have a look at it
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<thardin> sweet, adding registers inbetween stages in my design speeds it up (at the cost of total delay)
<thardin> increases throughput that is
<thardin> which is what I'd expect
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