clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<cr1901_modern> Shouldn't the placer/packer give up after a finite time?
<cr1901_modern> Or is it only routing the gives up after finite time?
<mwk> from experience, routing does not give up after finite time
<mwk> (it does print information in the loop, though)
<mwk> a single iteration taking unbounded time is more worrying, though
<cr1901_modern> Could've sworn it used to... at least from attempting to route riscv designs into up5k
<cr1901_modern> But hey no big deal if I misremember lol
* mwk tortured both router1 and router2 with her shit database last two months, they both get stuck in infinite routing loops
<cr1901_modern> what's the difference between the two?
<mwk> router2 is the new experimental thing
<mwk> designed for large fpgas
<mwk> router1 is the original algorithm
<mwk> (and still the default)
<cr1901_modern> Ack... that makes sense... one of the major gripes with arachne, among others, was that it didn't scale
<porglezomp> I'm trying the SA placer now instead of the heap placer to see if that gets a chance to make progress
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<daveshah> porglezomp: if you are checking the backlog, there is supposed to be a timeout for the usual cases where placement gets stuck (usually unsolvable constraints)
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<tnt> Is it just me or does ABC9 for the ice40 really bad ?
<tnt> Super simple comb design, 4 * 13 bits comparator and a final AND: Doing it in my head: 37 LUT4s and depth=4. yosys, 40 LUT4s and depth=4, yosys+abc9 63 LUT4s and depth=4 ....
<tnt> So it completely exploded the usage for no gain whatsoever in critical path.
<tnt> Is there a subtle difference between |sig and sig[0]|sig[1]|sig[2]|sig[3] assuming wire [3:0] sig; ? Yields different results ...
<porglezomp> Different results in ABC? I'd expect it to be represented as the exact same canonical form.
<tnt> different synth output.
<ZirconiumX> tnt: it's a known issue, but we don't quite know why
<tnt> ZirconiumX: you mean the '|' or the abc9 explosion ?
<ZirconiumX> I do know the testcase I first found the issue with seems to have improved with very latest master (I think the ABC9 specify branch might have fixed it)
<ZirconiumX> ABC9
<ZirconiumX> I wrote a script to compare performance between two branches
<ZirconiumX> I should probably make it more fine-grained
<ZirconiumX> Well, I published it at least, so there's that
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<Sarayan> what is this "abc" stuff?
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<ZirconiumX> Sarayan: ABC is the program that performs gate to LUT conversion for Yosys
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<cr1901_modern> there is an experimental pass to get rid of ABC/do the conversion inside yosys (forget the name)
<ZirconiumX> FlowMap
<ZirconiumX> Well, there's also gate2lut, but that's not really recommended
<ZirconiumX> I mean, calling FlowMap experimental is not entirely accurate
<ZirconiumX> The core pass is pretty well tested
<ZirconiumX> It's just a lot less efficient than ABC because it's missing area recovery heuristics
<ZirconiumX> So the resulting netlist is bigger and thus slower because of the increased routing contention
<Sarayan> hmmm, abc, it's logic tree to luts or it's moe than that?
<Sarayan> more
<ZirconiumX> It's not just logic trees to LUTs; it can also do ASIC cell mapping, but the relevant bit here is logic tree to LUTs
<daveshah> It also does some other significant optimisations (removing redundancy etc)
<ZirconiumX> FlowMap is not *that* bad for how little it does in comparison
<ZirconiumX> But the state of the art has definitely moved on since the 1990s
<daveshah> No, although as you've identified previously runtime may be a bigger issue than QoR
<daveshah> Runtime is generally something that has a lot of scope for improvement in Yosys imo
<daveshah> parellelised "noflatten" (or flatten-at-fine-grain) flows being one of the most significant pieces of low hanging fruit
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<lambda> how well do out-of-context runs work with yosys? is it as simple as synthesizing modules with -noiopad, writing the result out to json/blif/whatever, then read_*'ing them back in before synthesizing the main design?
<daveshah> You are probably going to have most success doing this with either ilang or json
<daveshah> Definitely not blif, blif is horribly lossy in a modern synthesis environment
<mwk> lambda: we use OOC mainly for tests and/or benchmarks, but they way you described should work
<mwk> (please report if you run into problems)
<lambda> daveshah: ah, good to know
<ZirconiumX> I'd recommend ilang personally
<lambda> mwk: I'd use it to reduce synthesis times a bit, since the big modules (ethernet, dram) don't usually change during development
<lambda> PNR is still the biggest time sink, but since it's fairly atomic there's not much I can do about it anyway
<ZirconiumX> You need a bit of prep work to use it though
<daveshah> There may be a nextpnr issue to do with timing analysis and dangling logic that I've been meaning to look into that will be triggered by this
<lambda> right now I have to figure out what broke my UART anyway, it was more of a question about future possibilities because I got frustrated with spending >50% of my time waiting ;)
<ZirconiumX> I mean, Yosys is fairly fast as an EDA tool; think about that
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<lambda> oh definitely, I don't even want to think back to the dark times of vivado - but still, if there's a chance to make it even faster, I'll look into it
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<Sarayan> ~~~~/jmi
<Sarayan> gah
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<tnt> Does yosys have a command to output the max comb depth ?
<ZipCPU> tnt: Check out ltp
<tnt> ZipCPU: perfect !
<tnt> tx
<corecode> tnt: i'm watching your cache stream
<corecode> thanks for that, it's nice to see the thought process
<corecode> what do you use to draw?
<tnt> corecode: https://remarkable.com/ and since it runs linux, I created a small software that grabs the frame buffer and streams it over its usb port for live streaming.
<corecode> aaah
<corecode> yea it's quite pricy :/
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<tnt> yeah :/ no doubt about that.
<corecode> thanks
<corecode> i draw in notebooks, but then the drawing lives on a different place
<tnt> I used to draw in notebooks too and I got this to be more organized and then I can grab some of the diagrams and put them along with the code. A bit like I did here https://github.com/Spritetm/hadbadge2019_fpgasoc/blob/master/doc/audio/synthesizer.md
<corecode> i guess for that taking a picture sort of works
<tnt> yeah sure, svg is just nicer :p
<corecode> oh those are svg
<corecode> nice
<ZirconiumX> tnt: Check out Eddie's sta branch; it takes into account timing for longest combinational path
<ZirconiumX> Might be what you're looking for, might not
<qu1j0t3> /b 3
<corecode> tnt: i found the stream extremely easy to follow, even on 2x
<corecode> i did approach calculating the number of bits differently tho
<tnt> corecode: yeah, I'm not talking super fast since I'm actually thinking / designing in my head at the same time.
<corecode> nono, no criticism
<corecode> i watch everything on 2x
<corecode> listening is much easier than talking
<corecode> i don't think you're slow
<corecode> i wanted to indicate that your explanation was so clear that it was easy to follow
<tnt> tx
<corecode> almost makes me want to go back to my forth cpu and optimize it
<tnt> hehe :)
<corecode> i did it microcoded instructions, but that made them real wide
<tnt> yeah, the trade off between super wide and more complex decoding logic is always tricky.
<corecode> i might be able to squeeze in 2-3 instructions per word, but then i have a cycle latency on jump or immediate or memory access
<corecode> i think i got it running at 24MHz single cycle issue
<corecode> no pipelining, so limited by the data path mux
<tnt> That's pretty good for single issue.
<corecode> there might be ALU optimizations possible
<corecode> i hope i'm not lying
<tnt> I'm actually looking at some yosys synth result right now ... it's still fairly easy to do better than it manually ...
<corecode> i think i tried and synopsys wasn't much faster
<tnt> oh yeah, they're pretty much all equally dumb.
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<corecode> finally nextprn and trellis compiled
<corecode> 32MHz it says
<corecode> single cycle, single issue core
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