<dh73>
Yosys ABC scripts are not fully optimised. You can get better results by changing the scripts or saving the previous results and do a second or more runs over those results.
<ZirconiumX>
"have you tried running it again?" - the script
<dh73>
:P
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<ZirconiumX>
Hmm, while &lf is much smaller, it's worse in Fmax.
<ZirconiumX>
Can't have your cake and eat it too
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<ZirconiumX>
dh73: and it actually works, too. thanks, I hate it.
<ZirconiumX>
Like, that's an average 6 MHz over the default
<ZirconiumX>
And smaller.
<ZirconiumX>
tnt: turns out the solution to your problems is to just keep running ABC again until it works /s
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<tnt>
ZirconiumX: I had tried abc2 (to run it twice) and that didn't change thing. abc9 on the ice40 is just broken.
<tnt>
Now that I have added other logic (unrelated to those two signals, but using the same intermediate signals), it produces something different ... still not what I'd like and too long a path, but it's way less obvious what it's doing now.
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<tnt>
Is there a way to have "default" port value if an input port is not connected ? I tried something like `assign (weak0, weak1) port_in = 0;` but yosys doesn't seem to like it.
<thardin>
you mean like a pull-up?
<mwk>
tnt: do you mean a top-level module port?
<mwk>
if not, there's no way in yosys AFAIK
<tnt>
mwk: no, internal modules.
<tnt>
thardin: sort of except it's resolved at build-time, not runtime. When instanciating the module if that port is left unconnected, it takes that value instead of xxxx
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<Degi>
I'm getting a nextpnr_ecp5::assertion_failure (from nextpnr.h_362) when I try to do something with an ECLKSYNCB
<tnt>
Degi: and your treillis/database and nextpnr are all up-to-date ?
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<Degi>
Yes they seem to be, at least pacaur says that it is up to date (using the nextpnr-git and trellis-git package which directly reference the git repo)
<Degi>
though I found out that CLKDIVF also causes that
<Degi>
Basically it contains a single file which downloads trellis from github and then compiles it, so it should be up to date
<tnt>
and you did that recently ? And rebuilt nextpnr after any trellis update ?
<Degi>
Hm maybe I should try that and generally updating my computer...
<daveshah>
My gut feeling is that something that's supposed to be a string isn't
<tnt>
ah the famous lattice numbers as string "0b1010101" thing.
<daveshah>
There should be a better error but it may have been lost during the JSON format change
<daveshah>
The CLKDIVF division factor is a number like "2.0" in a string iirc
<Degi>
Oh
<Degi>
Now it works
<Degi>
Thanks!
<tnt>
IS yossys supposed to trim modules (in this case SPRAM) that I instantiate manually ?!?
<daveshah>
Yes, unless they are marked keep
<tnt>
and what criteria does it use ? I don't see anything in the output related to that instance at all.
<daveshah>
Some modules that you would not want trimmed (like WARMBOOT) are marked keep
<daveshah>
If it is not marked keep as a module and has no used outputs then it is trimmed
<daveshah>
Any module that "does something" even if no outputs are used should be marked keep in the library so this doesn't happen
<tnt>
ok, "no output" at least that gives me a hint as to waht's wrong. Thanks !
<Degi>
Hm is DLLDELD not yet implemented?
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<tnt>
Arf :+ vs +:
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<tnt>
Ohhh, yosys implemented a 4:1 mux in a way I had never thought of before using only 2 LUT4s in 2 layers. (instead of the "tree" structure of 2 * 2:1 + 2:1 that would use 3 LUT4s).
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<Degi>
Huh, the log says that DLLDELD exists (but 0 used) but something is giving me a "not part of the design" error
<tnt>
Looks like DLLDELD isn't defined in yosys
<Degi>
Hm yeah, I'll try updating it
<tnt>
No, even in master it doesn't seem to be.
<tnt>
where did you see that DLLDELD exists ?
<tnt>
AFAICT there is no support for it in either yosys or nextpnr yet.
<daveshah>
From memory DLLDELD is in Trellis but nothing else yet
<Degi>
Oh
<Degi>
Nextpnr says in the log that 0 DLLDELs are used, so I guess nextpnr supports it at least?
<daveshah>
No it doesn't, it just picks it up from the Trellis db
<tnt>
It knows it exists from the trellis database
<daveshah>
I can add support for it on Friday if you need it
<Degi>
Hm the reference implementation for the DDR aligned interface uses it, though I guess I could try using ddr centered, though that'd need a tx centered
<daveshah>
Ah right I hadn't seen that before, I usually just use delay blocks and hope for the best
<Degi>
Ah yes I guess I could do that too
<Degi>
Hm how do I make a 1 ns delay block?
<tnt>
DELAYG blocks
<daveshah>
With a value of about 25 (its circa 40ps per tap iirc)
<tnt>
Degi: note that depending on you interface, the clock signal might already be delayed compared to the data.
<tnt>
It takes more time for the clock to go from the pin through the buffer, through the cock network and to the IO FFs than for the data signals to go from the pad to the IO FFs.
<Degi>
In this case it shouldn't be, but for later usage yes
<tnt>
about 2ns
<Degi>
Hm oh
<Degi>
I couldtry if thats enough
<tnt>
*clock ...
<daveshah>
Unfortunately nextpnr and trellis don't have full IO timing support yet
<daveshah>
This is on the TODO list but a bit of a limitation for this kind of stuff
<tnt>
There is this weird zone. Between the slow interfaces where you can just use the opposite edge because they're slow enough. And there is super high speed stuff that needs runtime read training. And then there is in between where you do static io timing. That last one is definitely not ideal right now, always have to run some diamond / icecube to check.
<Degi>
Hm it says that DelayG must be connected to a top level input or output, the input is connected directly to a differential pair
<tnt>
for diff pair you would only use the _p signal and just specify the iostandard in the constraints.
<daveshah>
Also, you mustn't have any non delayed users of the signal either
<Degi>
Currently I'm doing it in nmigen so I basically have platform.add_resources([Resource("clkin", 0, DiffPairs("J_33:14", "J_33:13", dir="i"), Attrs(IO_TYPE="LVDS", DIFFRESISTOR="100"))])
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<tnt>
Err ... you'd have to check the RTIL generated by nmigen to see wtf it's doing and how to fix it.
<tnt>
you might have to use dir="*"
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<tnt>
sorry, dir="-"
<Degi>
Oh I was using the pin somewhere else, nvm
<Degi>
Cool it works
<Degi>
Does the refclk for the ODDRX2F need to be double the sclk frequency?
<tnt>
ECLK = 2 * SCLK
<tnt>
That's a 4:1 serdes, not a simple DDR.
<Degi>
Hm yes and since its routed over the edge clock, nextpnr doesn't complain about the frequency
<Degi>
Huh twisted pair arduino cables seem to have some crosstalk between clock and data at 1.2 Gbits
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<daveshah>
Interestingly, this semi-internal document suggests regular ddr modes have a higher max frequency in practice than x4
<daveshah>
Regular DDR worked on 100% of devices at 1300Mbps
<daveshah>
(spec 800Mbps)
<daveshah>
The 4:1 had 50% of devices failing at 1000Mbps
<Degi>
Hm yes DDR over arduino jumper wires seems to sporadically work at 1500 Mbps
<Degi>
Oh wtf I selected the wrong pins and wondered why it wasnt working. Apparently 720 Mbps works sporadically wirelessly
<daveshah>
lol
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<ZirconiumX>
Oh, hey phire
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<awygle>
lol hey phire. small world.
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<pepijndevos>
lolwat... wireless DDR?
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<tnt>
ac coupling
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<corecode>
tnt: now if you would do a stream about using formal, that would be great
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<phire>
oh yeah. I've been ideling in this channel for years
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<tnt>
corecode: you have to ask matt venn for that :) My formal knowledge is minimal at best and when I tried I kind of hit the limits of the oss version :/ (and yeah I know I can get a "hobby" license for the closed parser but that's just not the same)
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<corecode>
yea
<corecode>
maybe somebody can pick it up
<corecode>
the cache seems small enough to be able to understand the reasons on why to test something
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