clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<meawoppl> greetings humans!
<meawoppl> happy quarantine?
<meawoppl> ugh
<meawoppl> anyway
<meawoppl> I came here hoping to ask some things about the SPRAM on the ice40 chips
<meawoppl> I am getting something that works in simulation and diverges in FPGA behaviour
<meawoppl> and I was curious what timing/clocking requirements were in there that I might not be understanding properly
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<daveshah> There was a recent fix to the sim model relating to chip select
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<daveshah> Otherwise, if the design passes timing, it should also work in hardware
<meawoppl> I don't think my simulation has accurate timing honestly
<ZirconiumX> Hmm? How do you mean?
<meawoppl> rather I should say I am just using `iverilog` to compile it with the `cells_sim.v` file from yosys
<meawoppl> I guess what I am trying to understand is how timing info propogates from that file forward
<meawoppl> This block specifically:
<ZirconiumX> meawoppl: I'm...reasonably sure icarus doesn't care
<ZirconiumX> It would need a lot more information than just the Verilog source to be fully time-accurate
<meawoppl> yeah, I think it ignores the timing whatnot
<ZirconiumX> (the units are picoseconds by convention)
<meawoppl> gotcha, the yosys synthesis uses those values in the computation of the clock frequencies?
<ZirconiumX> ABC9 uses it to measure path criticality
<ZirconiumX> Amongst other things
<meawoppl> gotcha
<meawoppl> so, do I read this correctly that DATAOUT is undefined for 1821ps following a clock:
<daveshah> Yes, although if you look at the original data it's more accurately undefined between 675ps and 1821ps after a clock
<daveshah> But nextpnr should be taking this into account when calculating Fmax anyway
<meawoppl> gotcha
<meawoppl> I understand now that my `iverilog` treatment made the DATAOUT signal immediately valid
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<lambda> is there a way to read EDIF files back into yosys?
<daveshah> No, I don't think there is an open source EDIF frontend
<lambda> hm, that's unfortunate - seems like I found some bugs with EDIF output (or vivado at least understands it differently), reading it back and synthesizing with nextpnr would've been helpful for testing
<lambda> any other format yosys can output and vivado can read?
<daveshah> Verilog should work
<lambda> right, sure
<lambda> yeah, definitely multiple incompatibilities with EDIF even for a very simple design.
<daveshah> Are you using write_edif
<daveshah> You need to use write_edif -pvector bra
<lambda> oh, that may have helped. but I think there were other issues as well, particularly vector ports defined as [7:0] being indexed as [0:7] in the EDIF, causing everything to be the wrong way around
<lambda> (and differential ports not working at all because the positive and negative ports were also reversed)
<lambda> hooray, my DVI output works when I synthesize with vivado - must be something with nextpnr then, I'm guessing the TMDS33 differential outputs.
<daveshah> TMDS33 isn't supported
<daveshah> I don't even think Xray has the bits for it
<lambda> ah, fair enough.
<lambda> I don't really need it anyway, it's just nice for demo purposes, and running a netlist through vivado is absolutely fine for those few times
<daveshah> At low resolution using two LVCMOS33 outputs with inverted data (inverted at the OSERDES input) might work
<daveshah> *inverted data on the negative side
<daveshah> I've done this on the ECP5 in the past
<lambda> not actually using a SERDES, which would make that even easier
<lambda> (250MHz is still doable with a decent margin)
<lambda> on the other hand, that added inverter might cause some delay between positive and negative
<lambda> oh, just buffer it, duh. I think I'd rather do it properly or not at all though, and as long as nextpnr doesn't error because of the unsupported outputs it doesn't really matter
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