clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<awygle> hm what's a good speed to run an ecp5 at
<awygle> 120 MHz? 180?
<awygle> 240?
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<shapr> awygle: 45mph is the speed limit
* shapr is tired and silly
<awygle> lol hey shapr
<shapr> howdy awygle, how you doin?
<awygle> i've been better
<shapr> oh, what's up?
<awygle> but hanging in there
<awygle> i live in the Seattle area, so things are a bit crazy here atm
<shapr> you dropped off irc for a year or so, life happenings?
<shapr> ohh
<awygle> i did do that yeah. mental health stuff, which i'm happy to report is _much_ better
<shapr> glad to hear that
<awygle> how have you been?
<shapr> similar happenings, on call made me crazy, I quit my job in April, spent six months at recurse center, and just now have a Haskell job in Boston
<shapr> I've been here a month, it's a blast
<awygle> nice!
<shapr> But I'd also like to get yosys doing xilinx 7 stuff on this NeTV2 I got from bunnie's campaign
<shapr> though I hear from daveshah et al that xray won't be done for months
<shapr> and especially not for the 100T chip in this NeTV2
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<shapr> awygle: did you change jobs in the past year or so?
<awygle> it's been about 3 years since i did that i think
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<awygle> although i may have updated my linkedin in the last year or so :p
* shapr looks
<awygle> purely out of laziness
<shapr> ack, I haven't looked at linkedin in some time
* shapr digs out from under a pile of notifications
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<awygle> where does ecppack come from? trellis, presumably?
<ZirconiumX> Yeah
<awygle> it doesn't seem to handle 12Fs correctly
<awygle> in that... it doesn't handle them :p
<ZirconiumX> ...Because 12Fs are 25Fs
<awygle> this is because they're 25Fs, yes
<awygle> but they have different IDCODEs
<ZirconiumX> Which you handle at the programming stage
<awygle> ecppack outputs an SVF
<awygle> which expects the correct IDCODE
<awygle> afaict
<awygle> at any rate programming with openocd is failing with "WANT: <25F IDCODE> READ: <12F IDCODE>"
<awygle> updating trellis to see if that fixes it
<awygle> it does not
<awygle> overriding the IDCODE in the ecppack command line does work correctly, so that's good
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<awygle> actually i think the problem is in nextpnr so i'll update that too...
* shapr asks awygle to connect on the embedded network
<shapr> yay
<shapr> I'm gonna bet I have the largest number of linked in endorsements, for cartwheels
<awygle> updating nextpnr does not fix it, filed a bug report
<awygle> adding the override to my local copy of nmigen and moving on with my life
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<whitequark> it's weird that the FOSS toolchain approach to market segmentation is "expose the lie to everyone who needs to use the chips"
<whitequark> there's no "use 12f" switch. every single person who wants to use 12f's has to go through discovering this, rather painfully too
<whitequark> nmigen has a very nice table that makes it *especially* obvious in the platform code
<awygle> yep
<awygle> do you want me to upstream this into nmigen? think i can make it fit into the template so it's non-disruptive
<whitequark> if it's a nextpnr bug it should be fixed in nextpnr
<whitequark> it could be also fixed in nmigen temporarily to reduce the disruptiveness
<whitequark> but with emphasis on former
<awygle> definitely
<awygle> guess i'll wait and see whether anybody has a comment on the nextpnr issue. i'm utterly unfamiliar with that codebase and don't really want to try to push this uphill there right this second.
<whitequark> ime nextpnr bugs are fixed exceptionally quickly
<whitequark> so i don't usually bother with workarounds
<awygle> mk, noted. i'll hope to have the same experience
<awygle> hm now how do i program attached flash with openocd instead of the internal sram cells...
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<whitequark> i think you might need a proxy bitstream
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<awygle> looking like it yeah
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<tnt> Huh yosys sees a path (when doing ltp) from a SB_RAM40_4K write enable to the read data port ...
<tnt> (which means in a full design where the read data influences what you do next, it finds a loop ...)
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<corecode> is the write enable a write/nread?
<tnt> Shouldn't matter, they're registered. write enable is not going to influence the read data until the next cycle.
<sensille> could also be that if read and write address are the same, the write data shows up on the read port in the same cycle
<tnt> Also read / write ports don't even use the same clock ..
<tnt> All write are registered.
<corecode> oh i didn't read right
<corecode> the bram, not the spram
<corecode> i'll have to watch your video to find out more :)
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<tnt> Actually, I'm not even sure if ltp knows about clock / registers etc at all ... I might be expecting too much.
<daveshah> No it doesn't
<daveshah> You have to use the Yosys selection syntax to exclude these cell types
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<tnt> daveshah: you don't happend to have an example ? syntax is rather obscure. I tried "ltp */t:SB_LUT4" but that doenst' seem to work.
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<daveshah> I think if it is a flattened design the */ isn't needed
<daveshah> I don't have an example to hand though
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<tnt> Ok, I think I got it: ltp t:SB_DFF* t:SB_SPRAM256KA t:SB_RAM40_4KNW %% %n
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<tnt> tx for the tip !
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<pepijndevos> daveshah, could you maybe have a quick look at this PR? https://github.com/pepijndevos/apicula/pull/10 they are seeing it as a binary string, while I think it's supposed to be an int: https://github.com/YosysHQ/nextpnr/blob/bb7358020928d0a26ab7becd123ccdc15b0206cb/generic/cells.cc#L119
<daveshah> I think the Python API converts params to a binary string
<daveshah> JSON style
<pepijndevos> huh... odd... is that a recent change? The code I wrote assumed ints, and that used to work.
<daveshah> Not that recent, a good few months ago
<pepijndevos> More recent than the last time I compiled a new nextpnr and tested apicula apparently, which is indeed a good few months ago.
<pepijndevos> Thanks for the info, will merge these changes then, and not waste time digging in wtf was going on haha
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<Degi> Hm somehow the newest yosys build seemss to fai with "No rule to make target 'echo-abc-rev'", installed from the arch aur, here's the install script https://aur.archlinux.org/cgit/aur.git/tree/PKGBUILD?h=yosys-git Did anything change recently?
<daveshah> There was some activity recently, I think the broken commit has been reverted now though
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<lambda> daveshah: actually, the commit that added the functionality was reverted :)
<awygle> daveshah: any chance you can confirm whether https://github.com/YosysHQ/nextpnr/issues/409 is a nextpnr issue or a trellis issue? just wanna make sure i filed it in the right place
<daveshah> awygle: it's both, now that I'm free from political control from Edmund I'll deal with it
<awygle> okay, cool :) thanks
<awygle> (no rush or anything obv)
<daveshah> It certainly wasn't an oversight previously, it just got forgotten about
<daveshah> subsequent to my departure from seda
<awygle> sure
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<Degi> Hm it still gives the error, more specifically "fata: empty string is not a valid pathspec. please use . instead if you meant to match all paths" while executing git checkout "$(make --silent -C "${srcdir}/yosys" echo-abc-rev)"
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<ZirconiumX> Try a `make clean` before rerunning `make`
<Degi> Well I deleted the whole directory and redownloaded it, I guess the pkgbuild is broken
<Degi> Hm I'll just delete the echo-abc-rev from the pkgbuild and see what happens
<Degi> Well now it works
<Degi> Yeah somebody added that in an update 5 hours ago which apparently broke the AUR package.
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<lambda> Degi: my PR adding echo-abc-rev was accepted, then thasti updated the PKGBUILD to use it, then it was reverted.
<Degi> Hm oh. Yeah I just deleted that part from the PKGBUILD and now it works just fine
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