<tpb>
Title: GitHub - AmeerAbdelhadi/Verilog-Quartus-Mapping-VQM-Netlist-Parser: generates a Comma-Separated Values (CSV) file of all nodes in a given Verilog Quartus Mapping (VQM) netlist and their respective fanouts, ordered by fanout (highest first) (at github.com)
<peepsalot>
not sure if anything insightful from that
<peepsalot>
ZirconiumX: so would EDIF be the more of the preferred route for interfacing with Quartus, as an "open" standard?
<ZirconiumX>
peepsalot: As I mentioned, you need to figure out what dialect of EDIF we have, and that's even less documented
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<peepsalot>
man, i just read though the EDIF wikipedia page, sad...
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<ZirconiumX>
Hi peepsalot
<peepsalot>
hi
<ZirconiumX>
I think we're probably targeting VQM
<ZirconiumX>
Since it mostly just requires hacking write_verilog
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<Sarayan>
yosys barfs on existing sv code (fx68k, a 68000 sv reimplementation), it doesn't seem to like typedef struct { ... }. I've heard there was plans to change of parser, is that true?
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<Sarayan>
(also, hi :-)
<ZirconiumX>
Well, Yosys has Verific support, but then you need a Verific license for that
<ZirconiumX>
Which you probably can't get
<Sarayan>
probably not indeed
<Sarayan>
so the way forward is what, extend the existing parser or see if working with verible is possible?