clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<dormito> anyone seen yosys-abc abort on certain inputs?
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<attie> it might be fixed or it might still appear in different cases. this bug is one of those elusive ones that go away if you change one wire in your design
<dormito> I can build project trellis's picorv32_versa5g, and the tinyFPGA BX bootloader.
<dormito> I didn't change either design
<daveshah> I can't see any obvious commits in abc that might fix the problem beyond the revision Yosys uses
<dormito> and yeah. the issue seems to what I was running into
<daveshah> Oh, actually, there is a "fix" that Yosys misses
<tpb> Title: Temporary commenting out of the assertion. · berkeley-abc/abc@53f2238 · GitHub (at github.com)
<dormito> lol, they just disable the assertion?
<attie> hahaha
<daveshah> yes, that appears to be it
<attie> I guess that "works"
<daveshah> I guess the Yosys abc version should be bumped anyway
<dormito> I don't know jack about their code.... but it builds... so maybe it's correct?... one can hope
<daveshah> abc does have quite a few assertions that are about optimality rather than correctness, and this looks like one of them
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