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<Duality>
hi
<Duality>
is there any feasable way to revers a fpga bitstream image ?
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<ZipCPU>
Duality: Absolutely!
<ZipCPU>
Which tool you need and use, however, will depend upon which FPGA type you are working with
<ZirconiumX>
Or at least which FPGA family
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<ZipCPU>
As an example of what you might do with such a reversed capability, this project (https://github.com/ZipCPU/cputest-harness) takes an iCE40 image containing a RISC-V computer, adds a simulation for a QSPI flash and a serial port to it and allows you to interact with it
<tpb>
Title: GitHub - ZipCPU/cputest-harness: A simulation test harness, containing serial port, QSPI flash, and an output done I/O--just provide the CPU (at github.com)
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<flokli>
woah, very cool :-)
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<az0re>
Wait wait wait: You give it a complete iCE40 bitstream and it reconstructs the hardware it implements and adds a testbench around it, replacing actual FPGA I/Os with auto-generated testbench peripherals?
<az0re>
How does it recognize which FPGA I/Os are which peripherals? Do you need to have some hardcoded signal names in a .pcf or something?
<tpb>
Title: hay ball Blank Template - Imgflip (at imgflip.com)
<flokli>
:-D
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<ZipCPU>
az0re: There's a PCF file in the project directory that can be adjusted to make sure the I/O's are properly mapped
<ZipCPU>
But, yes, I "give it a complete iCE40 bitstream and it reconstructs the hardware it implements and adds a testbench around it, replacing actual FPGA I/Os with auto-generated testbench peripherals."
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