clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<sensille> daveshah: one intermediate result: if i don't use the uppermost bit of the ram, yosys doesn't infer block ram, with the same reason that the read clock is 'async' (which it is not)
<sensille> that insight doesn't help me with my full design, though (yet)
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<sensille> ok, i also found an assign to 0 for a lower layer output, which yosys did not complain about (or not enough). without that, i now get bram
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<ZirconiumX> https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v#L529 <--- the `^ (Y ^ Y)` term seems very wrong to me; doesn't that simplify out entirely?
<tpb> Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com)
<daveshah> ZirconiumX: not if Y contains 'x' bits
<ZirconiumX> Ah, x-propagation
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<r_miller> Can anyone help me interpret this report from nextpnr? https://pastebin.com/Xx8BhZVU Seems to be saying that resetn is assigned to a global buffer but taking 3.9ns to be routed a long way across the chip (5,2) -> (22,27). Is this right?
<tpb> Title: Info: Promoting globals.. Info: promoting $abc$55324$n71 [reset] (fanout 358) - Pastebin.com (at pastebin.com)
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<ZirconiumX> r_miller: that's precisely *because* it's a global buffer, I'd imagine.
<ZirconiumX> ECP5 has GSR; if you don't care about portability use that instead of a power-on reset
<r_miller> Sorry should have said: this is ice40.
<ZirconiumX> iCE40 has pretty slow routing
<ZirconiumX> Depends on the chip family though; what's the exact chip you're targeting?
<r_miller> HX8k
<ZirconiumX> Hmm. Let's ask daveshah
<ZirconiumX> By the way, r_miller, when was the last time you updated your Yosys?
<r_miller> Yesterday!
<daveshah> The problem is that iirc the globals are only used for real flop reset signals, to avoid unroutability issues when they are driving LUTs
<ZirconiumX> ...autoname isn't helping much, then
<daveshah> and the path here seems to be a LUT input
<daveshah> using an active high reset to match the hardware might help
<r_miller> I noticed it says 'cen' not 'reset' on the promotion message.
<daveshah> Indeed, looks like it is being promoted as a clock enable rather than a reset
<r_miller> I'm using it like "always @(posedge clk) if (~resetn) begin ... end"
<daveshah> You might have more success with `if (reset)`
<r_miller> I've tried that too, but maybe I missed an instance somewhere?
<daveshah> and if you are using a clock enable too, reset needs to be gated by it (so `if (cen) begin if (reset) ... else ... end`)
<r_miller> Would the routing be quicker if I convinced yosys/nextpnr to treat it as a reset?
<daveshah> Probably not that much so
<daveshah> from memory the global buffer adds about 1ns anyway
<daveshah> and there is the routing to the global buffer input too
<r_miller> It's a delay generated internally by a counter, I guess I could have separate local ones instead of one global one.
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