<sensille>
this is with verilator. am i missing some verilog quirks?
<lambda>
thardin: I think all of those are still lacking in nextpnr-xilinx. I know DSP is not complete, haven't tested DRAM yet, but I think that has the highest chance of working out of those.
<thardin>
lambda: hm, ok
<daveshah>
litedram should work, but its a bit experimental
<daveshah>
multipliers work, other DSP functions don't necessarily
<daveshah>
no transceiver support at all atm
<thardin>
shame. but maybe one can rig a parallel interface with the I/Os
<thardin>
would it be possible to sponsor someone to take a crack at tramsceiver support?
<daveshah>
If you are talking a fully open source flow, the first step would be supporting them in prjxray
<thardin>
that's the RE stuff, right?
<daveshah>
Indeed
<daveshah>
mwk has also been doing some Xilinx RE but I don't know if she's looked at xc7 transceivers yet
<mwk>
not really, but they tend to go down quickly
<mwk>
it's just a bunch of attributes stored 1-1 into the bitstream
<thardin>
so I imagine
<daveshah>
If its anything like ecp5 the challenge is working out what those attributes actually do
<daveshah>
ie making a foss replacement to the Vivado wizard or whatever
<thardin>
seems the artix is a better deal than the kintex in terms of dsp/$
<mwk>
*shrug* a valid way is just making a known-good template with vivado and reusing its attribute set
<tnt>
sensille: if those two behave differently that look slike a verilator bug to me.
<tnt>
(the only diff is the begin/end right ?)
<thardin>
mwk: right, should be possible to nail down in a reasonable amount of time. I poked at installing vivado a while back, maybe I'll give it a go again
<mwk>
also, note that in the meantime, yosys + Vivado P&R is a path that should be fully working
<mwk>
(if you can figure out how to instantiate the transceivers, which shouldn't be that hard)
<sensille>
tnt: right, begin/end changes behavior. i can't get it fully to work at all, so i'm suspecting i'm doing something wrong
<thardin>
hum-hum.. if I can do multi-drop LVDS then this might just be feasible
<tnt>
m-lvds is a thing but it's a bit != from lvds (termination etc ...)