captain_morgan06 has quit [Quit: Ping timeout (120 seconds)]
captain_morgan06 has joined #yosys
vidbina has joined #yosys
vidbina has quit [Ping timeout: 240 seconds]
develonepi3 has joined #yosys
X-Scale has quit [Ping timeout: 260 seconds]
X-Scale` has joined #yosys
X-Scale` is now known as X-Scale
kraiskil has joined #yosys
kraiskil has quit [Read error: Connection reset by peer]
kraiskil has joined #yosys
vidbina has joined #yosys
vidbina has quit [Ping timeout: 260 seconds]
attie has quit [Ping timeout: 268 seconds]
kraiskil has quit [Ping timeout: 240 seconds]
vidbina has joined #yosys
ckqee has joined #yosys
<ckqee>
Hi
<ZirconiumX>
Hello
<ckqee>
:-) is this the right place to ask questions about yosys and nextpnr?
<ckqee>
I see an issue when installing nextpnr$ cmake -DARCH=ice40 .CMake Warning at /usr/local/share/cmake-3.16/Modules/FindBoost.cmake:2020 (message): No header defined for python-py369; skipping header check (note: header-only libraries have no designated component)Call Stack (most recent call first): CMakeLists.txt:157 (find_package)
<ckqee>
i am using Ubuntu 18.04.4 LTSI don't know how to over come the cmake issue
<ckqee>
according to the issue#87 - i cannot find "Did you run ./download-latest-db.sh inside the prjtrellis folder" from 2018 - looks like it does not exist any more
<daveshah>
Is cmake actually failing? What happens if you run make -j7
<daveshah>
The download-latest-db is no longer needed
<ckqee>
i get
<ckqee>
make -j`nproc`make: *** No targets specified and no makefile found. Stop.
<daveshah>
What is the full cmake output? You've only posted a warning not an error
<ckqee>
Makefile creation has not completed to what i understand it to be
<ckqee>
6.28 MiB | 5.39 MiB/s, done.Resolving deltas: 100% (11514/11514), done.user1@machine:~/github/YosysHQ$ cd nextpnr/user1@machine:~/github/YosysHQ/nextpnr$ cmake -DARCH=ice40 .-- The C compiler identification is GNU 7.4.0-- The CXX compiler identification is GNU 7.4.0-- Check for working C compiler: /usr/bin/cc-- Check for working C compiler:
<ckqee>
/usr/bin/cc -- works-- Detecting C compiler ABI info-- Detecting C compiler ABI info - done-- Detecting C compile features-- Detecting C compile features - done-- Check for working CXX compiler: /usr/bin/c++-- Check for working CXX compiler: /usr/bin/c++ -- works-- Detecting CXX compiler ABI info-- Detecting CXX compiler ABI info - done-- Detecting
<ckqee>
CXX compile features-- Detecting CXX compile features - done-- Found PythonInterp: /usr/bin/python3.5 (found suitable version "3.5.2", minimum required is "3.5") -- Found PythonLibs: /usr/lib/x86_64-linux-gnu/libpython3.6m.so (found suitable version "3.6.9", minimum required is "3.5") -- Looking for pthread.h-- Looking for pthread.h - found--
<ckqee>
Performing Test CMAKE_HAVE_LIBC_PTHREAD-- Performing Test CMAKE_HAVE_LIBC_PTHREAD - Failed-- Looking for pthread_create in pthreads-- Looking for pthread_create in pthreads - not found-- Looking for pthread_create in pthread-- Looking for pthread_create in pthread - found-- Found Threads: TRUE -- Found Boost: /usr/include (found version "1.65.1")
<ckqee>
found components: filesystem thread program_options iostreams system chrono date_time atomic regex -- Found OpenGL: /usr/lib/x86_64-linux-gnu/libOpenGL.so CMake Warning at /usr/local/share/cmake-3.16/Modules/FindBoost.cmake:2020 (message): No header defined for python-py369; skipping header check (note: header-only libraries have no designated
<ckqee>
component)Call Stack (most recent call first): CMakeLists.txt:157 (find_package)CMake Warning at /usr/local/share/cmake-3.16/Modules/FindBoost.cmake:2020 (message): No header defined for python-py36; skipping header check (note: header-only libraries have no designated component)Call Stack (most recent call first): CMakeLists.txt:164
<ckqee>
(find_package)CMake Error at CMakeLists.txt:199 (find_package): Could not find a package configuration file provided by "Eigen3" with any of the following names: Eigen3Config.cmake eigen3-config.cmake Add the installation prefix of "Eigen3" to CMAKE_PREFIX_PATH or set "Eigen3_DIR" to a directory containing one of the above files. If
<ckqee>
"Eigen3" provides a separate development package or SDK, be sure it has been installed.-- Configuring incomplete, errors occurred!See also "/home/user1/github/YosysHQ/nextpnr/CMakeFiles/CMakeOutput.log".See also "/home/user1/github/YosysHQ/nextpnr/CMakeFiles/CMakeError.log".user1@machine:~/github/YosysHQ/nextpnr$
<ckqee>
@daveshah - thank you for helpng me :-)
<daveshah>
You need to install eigen3
<daveshah>
and the development package for it, if applicable
<ckqee>
Thank you ! that worked did
<ckqee>
sudo apt-get install libeigen3-dev
<ckqee>
i spoke (typed) too soon -
<ckqee>
i now see the following
<ckqee>
[ 13%] Building CXX object generated/3rdparty/QtPropertyBrowser/src/CMakeFiles/QtPropertyBrowser.dir/qttreepropertybrowser.cpp.o[ 15%] Building CXX object generated/3rdparty/QtPropertyBrowser/src/CMakeFiles/QtPropertyBrowser.dir/qtvariantproperty.cpp.o[ 16%] Building CXX object
<ckqee>
i noticed some people write make -j`nproc` and some write make -j$(nproc)
<ckqee>
i was toying with the idea of using Vivado to view the schematic netlist out of yosys. - i have to create a Verilog simulation cell library that defines all the cells in a particular liberty.lib file
s_frit_ has quit [Remote host closed the connection]
<emily>
... is the old and mostly obsolete shell syntax
s_frit has joined #yosys
<ZirconiumX>
emily: I think half your message got cut off
<ckqee>
hmm -i am showing my age? :-|
<emily>
ZirconiumX: are you sure?
<emily>
I was responding to ckqee
<ZirconiumX>
"<emily> ... is the old and mostly obsolete shell syntax"
<tpb>
Title: #yosys on 2020-02-14 — irc logs at whitequark.org (at freenode.irclog.whitequark.org)
<ZirconiumX>
emily uses NixOS
<emily>
oh huh
<emily>
there were meant to be backticks around the ...
<emily>
I guess weechat-matrix messes it up :/
<ckqee>
i did not know about NixOS!
<ckqee>
learning something new :-)
<emily>
I use fish as my shell. it's not Bourne sh/bash/zsh/... compatible though.
<ZirconiumX>
You should always use $(...), especially since it's POSIX
<ZirconiumX>
And nestable
<ckqee>
i now understand
<ckqee>
one question about verilog if i may
<ZirconiumX>
emily: I really like fish and really hate fish at the same time >.>
<emily>
I've spent the past few minutes trying to dig up a citation for when exactly $(...) originates
<ckqee>
when you have a reg myregA = 0;
<emily>
since I'm curious now
<ckqee>
some asic tools complain right?
<emily>
ZirconiumX: what do you hate about it? most of the nits I had with it are fixed. I wish it supported subshells natively
<ckqee>
but FPGA tools seem to be ok with it?
<ZirconiumX>
That's not synthesisable for ASICs because ASIC flip-flops are not initialisable
<emily>
ZirconiumX: btw you can nest backticks, it's just horrible.
<ZirconiumX>
However, FPGA flip-flops are
<emily>
foo \bar \\\baz\\\\
<emily>
...
<ckqee>
what is the workaround to migrate the fpga code to asic?
<emily>
right, matrix.
<emily>
uh. hm.
<emily>
foo \bar \\\baz\\\\
<ckqee>
Thank you ZirconiumX
<emily>
if that didn't send properly then i don't care.
<ZirconiumX>
ckqee: Have a reset input, and then `always @(posedge clk) begin if (reset) myregA <= 0; else begin ... end end`
<ckqee>
Now that makes sense with what I am reading up on. so that coding style is specific to asic
<ZirconiumX>
It's feasible to do it on FPGAs too
<ZirconiumX>
It's just that FPGAs generally have first-class support for it anyway
<ckqee>
so we should write ASIC RTL Verilog for FPGA which can then be easily migrated to ASIC tools without too much hassle?
<ZirconiumX>
Like most things: it depends
<ckqee>
wow i like the nextpnr gui -
<ckqee>
is there a logic schematic capability in it?
<ZirconiumX>
You definitely *can*, but code that is optimal for ASICs will likely result in majorly slow FPGA logic
emeb has joined #yosys
<ckqee>
thank you all - my local build of nextpnr works!
<ckqee>
:-)
<ckqee>
@ZirconiumX where can i read up on this please?
<ZirconiumX>
For example, an ASIC library might want to manually instantiate a memory tuned to the process, which an FPGA synthesis tool would have to build out of flops
<ZirconiumX>
I don't know, ckqee; it's knowledge I've accumulated in the...year-ish since I picked up FPGas
fsasm has quit [Ping timeout: 272 seconds]
<ZirconiumX>
daveshah: So, I've been running Fmax tests with --randomize-seed, but not setting an Fmax target. Is that a valid testing methodology, or will nextpnr produce worse results without a proper Fmax target?
<daveshah>
it's just a default based on the most common iCE40 designs
<daveshah>
you can change the default for all clocks using the `--freq` command line argument too
<meawoppl>
OIC
<meawoppl>
how does yosys decide which lines are clocks?
<daveshah>
it's nextpnr that decides
<daveshah>
anything connected to a clock sink port is a clock
<daveshah>
(that could be of an FF, BRAM, IO, etc)
<meawoppl>
ahhh, so anything that appears in a `posedge` list plus async assignment?
<daveshah>
async resets wouldn't count
<daveshah>
but the clock part of any `posedge` list would
<meawoppl>
makes sense!
fsasm has joined #yosys
Cerpin has quit [Quit: leaving]
Cerpin has joined #yosys
<meawoppl>
As a followup question, is there a way to hint it in code about these speeds? At present, whenever I add an instance of this module, I will run into this issue...
<meawoppl>
I have 1 here, but I will have 144 in the next version
<daveshah>
No, not currently. 144 different clocks sounds like a bad idea too
<daveshah>
There are 8 global clock signals. Once you exceed that clocks end up being routed using general routing which can cause horrible skew and hold time issues
<meawoppl>
Noted! I will have to rethink the sampling logics then. It should be fixed in that version, so I can do some simplification I suspect
<meawoppl>
fixed meaning constant
<daveshah>
Depending on where the signal comes from, using clock enables is often a better idea than new clock signals
<meawoppl>
OIC, like sharing the came clock buffer, then switching in and out the pieces using it?
<daveshah>
Yes. Usually this would be code like `always @(posedge clock) if (clock_enable) do_something;`
<daveshah>
Instead for example of dividing `clock` by 4, you could have `clock_enable` high one every 4 cycles
X-Scale` has joined #yosys
X-Scale has quit [Ping timeout: 240 seconds]
X-Scale` is now known as X-Scale
rohitksingh has quit [Ping timeout: 268 seconds]
<peepsalot>
ZirconiumX: i downloaded your intel branch. is there any specific simplified test case I should try on de10-nano to see what the exact errors you are dealing with?
<ZirconiumX>
Unfortunately nothing "simplified"
<ZirconiumX>
But if memory serves me correctly - christ it's been a while - try compiling something for Cyclone V and using -vqm, and then try that under Quartus
<peepsalot>
I've seen Quartus has some options for external "Design Entry/Synthesis" tools, and there is a Custom option, but looks like specifying a command to automatically run a custom option is not supported?
emeb_mac has joined #yosys
az0re has joined #yosys
<peepsalot>
Also, it has choices of Format: VQM, Verilog HDL, AHDL, and VHDL. I wonder if Verilog HDL would be any more compatible than VQM?
<ZirconiumX>
peepsalot: Verilog mode *is* more compatible, but it's also notably slower
<ZirconiumX>
In VQM mode Quartus just parses the file and turns it into the Quartus internal database format
<peepsalot>
for VQM can it use any "atom"/primitive?
<peepsalot>
i don't have any projects to try but mister stuff :/ , which i guess is a mix of incompatible VHDL etc.
<ZirconiumX>
Pretty much
<peepsalot>
ZirconiumX: do you think it would help to have some EBNF checker/validator that could be run on yosys output against the VQM spec from that QUIP doc?
<ZirconiumX>
Doesn't that essentially boil down to "the Verilog specification"?
<peepsalot>
idk, i mean, its a specific subset, right?
<ZirconiumX>
It's still a pretty general subset of the language
<ZirconiumX>
The restrictions don't mean too much in the grand scheme of things
<Sarayan>
Hey ZX, aren't you drowing in gigabytes of text? ;-)
<ZirconiumX>
Sarayan: I am, but I believe somebody else was writing a database extractor :P
<Sarayan>
huhuhu yes, I'm doing too many things at the same time
<Sarayan>
found interesting information in there or not yet?
<ZirconiumX>
Not yet, what with about a million different people wanting me for different things
<ZirconiumX>
peepsalot: perhaps you should join us in #prjmistral
<Sarayan>
ZX: We have similar lives :-) RIght now I'm re-ing a cpu from 3 program dumps and nothing else