<tpb>
Title: `timescale 1ns / 1ps `default_nettype none /* * simple fifo. The next data - Pastebin.com (at pastebin.com)
<daveshah>
Seems to work fine here
<sensille>
strange
<daveshah>
Is this with default DATA_WIDTH and ADDR_WIDTH? if you overrode ADDR_WIDTH to be smaller Yosys might see it more efficient to use LUTRAM instead (but this would be a different message)
<sensille>
DATA_WIDTH=72, ADDR_WIDTH=9
<sensille>
also it _says_ it doesn't use bram because "Read port #0 is in clock domain !~async~."
<sensille>
dunno if that's the real reason, though
<sensille>
same problem with another ram
<sensille>
i'll reduce the design to something where bram still gets inferred and work up from that later, thanks for testing
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<janrinze>
daveshah: using DP16KD i get the data after the clock. if i just use an array in verilog i can get the data before the clock. how does yoysys/nextpnr setup DP16KD to achieve that?
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<janrinze>
daveshah: does yoysys 'smartly' implement a write to the 'read address' using substitution? thus assuring that the data is available on the next clock?
<tnt>
janrinze: what do you mean before the clock ?
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<janrinze>
tnt: DP16KD has a clock
<janrinze>
tnt: with reg[15:0] memory[0:8191] you can do 'always@* out=memory[address] ; always@(posedge clk) memory[address]=in;'
<tnt>
yeah ... and that's not going to map to a DP16KD
<janrinze>
tnt: it actually does.
<tnt>
unless `address` is a register
<tnt>
and then yosys will "move" the register.
<janrinze>
address is a register
<janrinze>
tnt: 'move' as in using the read address as the detination register?
<janrinze>
oops 'destination'
<tnt>
it will use the input to the address register (instead of the ouptut) to actually feed the address input of the DP16K read side.
<janrinze>
tnt: yup
<janrinze>
tnt: but how can i infer the same?
<tnt>
?
<janrinze>
tnt: with using the DP16K primitive?
<tnt>
That's not 'infer' ... 'infer' is letting yosys do it.
<tnt>
'instanciate' is doing it 'manually'.
<janrinze>
okay.. how can i get the same behaviour that yosys does ?
<tnt>
Well you need to change your HDL ...
<janrinze>
using DP16K
<tnt>
if you only have access to 'address' register output, you can't.
<janrinze>
yosys can but i can't.. i see
<tnt>
yosys has access to the whole design and can mangle it like it wants. You can't do that ...
<janrinze>
the 'move' magic would be very nice to have.
<janrinze>
same for the output register, ifr i clock that in then it will be 'late' by one clock..
<tnt>
yosys can add read bypass logic if need be.
<janrinze>
okay, yoysys can do some nice mapping and it will work on the proper clock transition. There aren't any verilog tricks to do the same, right?
<tnt>
well no ... you instanciate a blackbox, verilog has no clue what that black box does.
<tnt>
if it doesn't do what you need, tough luck, it's up to you to rewrite the logic around it so it fits your use case.