alexhw has quit [Remote host closed the connection]
fsasm has joined #yosys
piegames1 has joined #yosys
vidbina_ has quit [Ping timeout: 240 seconds]
fevv8[m] has joined #yosys
rjo has joined #yosys
nrossi has joined #yosys
ematrix has joined #yosys
pepijndevos[m] has joined #yosys
promach3 has joined #yosys
jryans has joined #yosys
indy has joined #yosys
develonepi3 has quit [Quit: Leaving]
captain_morgan20 has quit [Read error: Connection reset by peer]
captain_morgan20 has joined #yosys
oldtopman has quit [Remote host closed the connection]
captain_morgan20 has quit [Read error: Connection reset by peer]
_whitelogger has joined #yosys
vidbina_ has joined #yosys
emeb has joined #yosys
alexhw has joined #yosys
rohitksingh has joined #yosys
citypw has quit [Ping timeout: 268 seconds]
dh73 has joined #yosys
rohitksingh has quit [Ping timeout: 260 seconds]
vidbina_ has quit [Ping timeout: 258 seconds]
vidbina_ has joined #yosys
rohitksingh has joined #yosys
dys has quit [Ping timeout: 245 seconds]
bluesceada has quit [Remote host closed the connection]
bluesceada has joined #yosys
rohitksingh has quit [Ping timeout: 268 seconds]
jwhitmore has joined #yosys
attie has joined #yosys
[X-Scale] is now known as X-Scale
jwhitmore has quit [Ping timeout: 258 seconds]
attie has quit [Ping timeout: 260 seconds]
rohitksingh has joined #yosys
blackbit has left #yosys ["WeeChat 2.7-rc1"]
rohitksingh has quit [Ping timeout: 265 seconds]
dys has joined #yosys
rohitksingh has joined #yosys
cr1901_modern has quit [Read error: Connection reset by peer]
az0re has quit [Ping timeout: 240 seconds]
fsasm has quit [Ping timeout: 248 seconds]
cr1901_modern has joined #yosys
emily is now known as emilazy
ematrix is now known as emily
az0re has joined #yosys
dys has quit [Ping timeout: 260 seconds]
rohitksingh has quit [Ping timeout: 260 seconds]
emily is now known as ematrix
emilazy is now known as emily
emily is now known as emilazy
ematrix is now known as emily
emeb has left #yosys [#yosys]
awygle has joined #yosys
<awygle>
Can I communicate to yosys/abc/nextpnr that the calculation I've described must complete within X cycles of a Y MHz clock, please optimize it for area?
<tnt>
within X cycles ? nextpnr doesn't have multi-cycle constraint in the first place.
<daveshah>
Yeah, nextpnr doesn't support this yet
<awygle>
that's more or less what i expected
<awygle>
thanks tho
<awygle>
i was thinking maybe abc's "retiming" stuff could be used for this somehow
<daveshah>
You could probably give abc a delay constraint of X/Y
<sorear>
what tools *do* have that kind of multi-cycle constraint?
<daveshah>
But abc's delay constraints don't tend to yield vast area improvements
<daveshah>
At least some of the vendor onez
<tnt>
awygle: well it's not the same thing as retiming.
<daveshah>
*ones
<awygle>
another channel recommended trying vivado hls
<tnt>
that's _yet_ another different thing than multi-cycle constraints ...
<awygle>
tbf, i didn't say "multi cycle constraints", you did
<tnt>
retiming is moving pipeline register around to try and equalize the paths between FFs.
<sorear>
do you have throughput requirements?
<awygle>
you can see the relation though, yes? i want to add or remove pipeline registers to try to minimize total area. that the one might apply to the other is not a crazy thought.
<tnt>
multi-cycle constraint is allowing the comb logic to take more time between FFs than the normal clock period because you guarantee externaly, somehow, that the input is going to be state for N cycles on you will only clock enable the output after N cycles.
<tnt>
HLS will potentially generate completely different logic and data path and everything depending on a set of parameters.
<awygle>
sorear: kind of? i have a calculation, which must happen within (say) 16 clock cycles. after 16 clock cycles i should be able to launch the calculation again. that's all i really want.
<daveshah>
abc's retiming is pretty crap tbh
<daveshah>
There was talk of doing retiming in Yosys itself but that seems to have stalled, there isn't even a timing framework yet afaics
<tnt>
also in fpga, pipeline registers can often be free since they're already after each lut wether you use them or not.
<daveshah>
Yep
<daveshah>
I think doing post placement retiming in nextpnr could be interesting for larger devices
<daveshah>
Particularly once you get into Xilinx "3D" die crossing
<daveshah>
But that's a digression
<awygle>
I'll play with the hls stuff, see how that goes. Thanks all.
<tnt>
So realistically area really won't change drastically. If you have 16 cycles the only thing that would change it a lot is if you can do resource re-use / sharing without paying too much for the muxes needed for that, but no tool is going to do that for you, that's your job as the designer.
<awygle>
a tool absolutely should be able to tell me that, it's a completely deterministically knowable thing.