clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<rjo> i didn't see anything in the logs. maybe about fabric clock enables but not about the SB_IO
<rjo> daveshah: got a link?
<tpb> Title: yosys/cells_sim.v at 58ab9f6021bc5b90956d97759ef0f3bc8c7e209e · YosysHQ/yosys · GitHub (at github.com)
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<rjo> that ends with questions...
<daveshah> rjo: sorry, meant to link this one
<daveshah> The Yosys sim model should be correct
<rjo> ok. thanks!
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<heijligen> Hi, what does yosys mean by "Executing EDIF backend. ERROR: Don't know how to handle 1'z on (portRef (member gp0_out 0))."
<az0re> looks like you have some tri-state buffer it doesn't like
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<az0re> (just a guess; I'm not familiar with the EDIF backend at all)
<mwk> heijligen: what target is it? in general, 1'bz shouldn't survive until EDIF
<heijligen> my input are +/xilinx/cells/xtra.v and vhdl through ghdl
<heijligen> yosys -m ghdl -p "read_verilog +/xilinx/cells_xtra.v; ghdl --std=08 $^ -e top; synth_xilinx -top top -edif $@"
<heijligen> I'm trying to wrap the PS7 primitives into vhdl records
<heijligen> mwk: it's an Zynq7020
<mwk> heijligen: are you using the latest git yosys? there have been a lot of improvements to tristate support recently
<mwk> also, why are you manually adding cells_xtra.v? synth_xilinx should do it on its own
<heijligen> I'm using Yosys 0.9+932 (git sha1 8b2c9f45, gcc 8.3.1 -fPIC -Os), will rebuild and test with git master
<mwk> wait a moment
<heijligen> ok, that synth_xilinx is including the rechlibs wasn't known to me
<mwk> okay, you should still update
<mwk> but
<mwk> that seems to be new enough that tristate buffer is in, just not enabled by default
<mwk> try adding -iopad to synth_xilinx
<daveshah> I don't know if cells_xtra being read by synth_xilinx works here, if ghdl needs the blackboxes
<daveshah> (as synth_xilinx is after ghdl)
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<mwk> hmm, true, dunno about ghdl
<heijligen> I'll rebuild the toolchain and run it again
<heijligen> I've no inout wires in my design, so why should there something with a tri-state buffer
<heijligen> my code is at https://github.com/heijligen/vhdl_pynq, it's a simple blink example
<heijligen> blink is working, blink2 not
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<mwk> heijligen: could you run synth_xilinx without edif output, use `dump` to write the ilang file afterwards, then upload it somewhere?
<mwk> could be a missing wire somewhere
<tpb> Title: blink2.dump · GitHub (at gist.github.com)
<heijligen> the error by synth_xilinx -edif is ERROR: Don't know how to handle 1'z on (portRef (member gp0_out 106)).
<mwk> heijligen: uhh, this dump doesn't appear to even contain your module?
<heijligen> when i say "show top" the output is correct
<mwk> what about "dump top"?
<heijligen> I've updated the gist. there is mow a top
<tpb> Title: Pasteboard - Uploaded Image (at pasteboard.co)
<mwk> alright, so it seems that zynq_ps7 does something stupid
<mwk> gp0_out is connected to 'z
<mwk> or at least bits [77:66] of it
<heijligen> most of zynq_ps7 is not connected. I don't need it yes and leave the ports open
<mwk> it's about zynq_ps7 driving a 'z on some of *its* output ports
<heijligen> what does 'z mean? I'm relative new to this stuff
<mwk> hmm.
<mwk> well, 'z means unconnected
<mwk> ie. you're not assigning a value to some of the output ports
<mwk> well, undriven really, not unconnected
<mwk> you know what, I'll cook you a patch
<heijligen> ok, that is wat I wanted. this wires are there from the verilog module and i've wrapped them in vhdl and do not need them
<mwk> heijligen: try out mwk/edif-z branch of yosys
<mwk> I think it should be the correct fix
<heijligen> It's building successfully
<heijligen> mwk: the bitstream is working. thanks
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<DurandA59> Hi everyone. I have a quick question concerning Yosys: what are BUFs that are drawn everywhere from my design using the show command.
<ZirconiumX> Buffers
<daveshah> They are used for aliases between net names
<ZirconiumX> What are you targeting?
<daveshah> They aren't really cells in the netlist
<DurandA59> I am targetting ECP5 using Trellis. So this is just for the xdot representation and doesn't map to an actual element of the FPGA?
<daveshah> No, they don't have any relationship to FPGA mapping
<daveshah> They are really just giving an alternative name to a net, equivalent to "assign b = a;" in Verilog
<DurandA59> Thank you very much!
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