clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mwk> daveshah: any opposition to https://github.com/YosysHQ/yosys/pull/1673 from your side, or should I just merge it?
<tpb> Title: Add opt_lut_ins pass. by mwkmwkmwk · Pull Request #1673 · YosysHQ/yosys · GitHub (at github.com)
<daveshah> mwk: I haven't actually had a chance to test it yet. Does it ensure that mux structures for ECP5 are always still complete?
<daveshah> nextpnr-ecp5 currently requires this
<mwk> no, it can turn a LUT into a const
<mwk> if it's not depending on *any* inputs
<daveshah> Ah, that will break then
<daveshah> I can look at fixing the nextpnr side but can't guarantee that will be today
<mwk> hmm
<daveshah> Although it doesn't actually break
<mwk> I can just disable this part for ecp5 and emit an all-0 or all-1 LUT4 instead
<daveshah> It seems to be doing that already?
<daveshah> e.g.
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<mwk> oh
<mwk> it actually does that by an accident
<mwk> but yeah, it does work that way
<daveshah> Fine for me to be merged then
<mwk> (because the "pad to 4 if ecp5" code is before the "check if 0 inputs" code)
<mwk> I'll make this behavior more explicit
<daveshah> Thanks!
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<dkozel> Hi Folks. Just noticed that the sphinxcontrib-verilog-diagrams package is missing from pypi and cannot be installed (other than with git) via pip
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