clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<strongsaxophone> is there any control option to force yosys accept a file without error ( syntax error, unexpected TOK_ID)
<strongsaxophone> this error happend because of this part of code :
<strongsaxophone> >------->-------for (int i = 0; i <= 3; i++) begin
<strongsaxophone> >------->------->-------$display("register_file: register[%2d]: %2d",~
<strongsaxophone> >------->------->------->-------i, register[i]);
<strongsaxophone> >------->-------end
<daveshah> You could put the non synthesisable stuff in `ifndef SYNTHESIS
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<strongsaxophone> it worked, thank you.
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<peepsalot> ZirconiumX: a quick search for yosys+Quartus brings me to the vloghammer page, which has a bunch of stuff logged against quartus 17.0. are these part of what's blocking de10-nano progress?
<peepsalot> is there any reason not to test later version such as Quartus 19.1? or its just not been tried yet for time reasons
<ZirconiumX> peepsalot: vloghammer is a separate thing entirely
<peepsalot> i tried to install various older versions but the installer is bugged in mint/ubuntu and couldn't even get them to work properly
<ZirconiumX> peepsalot: so, Quartus has two kinds of file input types that we can produce
<ZirconiumX> A "Verilog Quartus Mapping" which is fairly strict subset of Verilog
<ZirconiumX> With terrible error messages because you're not supposed to get it wrong
<peepsalot> mapping full verilog to this subset of verilog? kinda transpiling?
<ZirconiumX> Well, the output is a netlist of Quartus cells
<ZirconiumX> It's like Verilog but if everything is a module
<peepsalot> ah ok
<peepsalot> and the second type?
<ZirconiumX> EDIF, which looks a lot like Lisp. Except it was very poorly specified and so compilers generally don't agree on what EDIF actually is
<ZirconiumX> The current Yosys write_edif is targeted for Vivado
<peepsalot> so you mentioned before that the netlist produced isn't compatible with Quartus for some reasons?
<peepsalot> does quartus netlist format need to be RE'd or something?
<ZirconiumX> peepsalot: It's very poorly documented, shall we say
<tpb> Title: synth_intel_alm: replacement flow for ALM-based Intel FPGAs. by ZirconiumX · Pull Request #1554 · YosysHQ/yosys · GitHub (at github.com)
<peepsalot> ZirconiumX: what is this "VQM Extractor and Language Functional Description, Version 2.0" mentioned in the comment? i couldn't find such a document
<ZirconiumX> "This excerpt from that document found in the QUIP latest release"
<ZirconiumX> Here probably referring to the Quartus University Interface Program
<tpb> Title: Download the QUIP ToolkitDownload the QUIP Toolkit (at www.intel.com)
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<peepsalot> yeah, i found the file in there, 15 yr old document is the latest?!
* GenTooMan just grins.
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