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<thardin>
has anyone tried to make red pitaya cores with yosys?
<thardin>
did a bit of searching around, but no relevant hits
<dys>
uuh, i don't think it supports Xilinx hardware? The Pitaya has a ZynC SoC…
<thardin>
uh I'm fairly sure I read it uses artix-7
<thardin>
maybe I read wrong tho
<daveshah>
There is some Zynq support with nextpnr-xilinx but probably not enough atm
<dys>
ooh, I seem to have missed the recent developments :-)
<daveshah>
Please don't actually try and use it :)
<daveshah>
It's very much hacker grade than end user grade atm
<dys>
ja, I guess the interfacing between the arm and the FPGA fabric on the SoC will still be a major problem even if the the fabric itself is supported
<daveshah>
That should work but has seen limited testing
<daveshah>
It's not very hard at all, just a load of wires
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<dys>
I was also thinking of the software-side. e.g. kernel drivers. what's a DMA IP core in the xilinx manual and a matching driver may need to be reimplemented in a compatible manner
<daveshah>
Oh yeah that's definitely something that needs to be opened up
<daveshah>
Particularly the BSP generator
<daveshah>
Stuff like dram init is doubtless super fun
<tnt>
I thought there was a free/oss fsbl for the zynq now ?
<daveshah>
Oh not sure, I haven't looked at zynq stuff for a little while
<tnt>
ah yeah, u-boot spl seems to be enough now.
<daveshah>
I think when I did zynq stuff building the fsbl still required some BSP outputs from Vivado
<daveshah>
> In order to replace the FSBL, U-Boot SPL requires to initialize the processor system using the hardware specific initialization code (ps7_init_gpl). These files are part of the Hardware Description File (HDF) created by the Vivado tool when exporting the design, and needs to be placed in the board folder within U-Boot code.
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<nanor00032>
questions about tcl support in yosys :
<nanor00032>
1) Is there a way to get a tcl shell to be able to work interactively in TCL (I'm using successfully TCL scripts already) ?2) IS there a native way to redirect the output of a command to a file ? (something like the 'redirect' command available in some tools)
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<attie>
Would yosys' `tee` command count as native?
<attie>
I'm not sure how/if that would work in tcl though, I've never used the tcl script interface...
<nanor00032>
Thanks ! I completly missed the tee command - I'm currently trying it - seems to work as expected in tcl mode
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<cr1901_modern>
daveshah: While it's on my mind, do you know when the pmgen tool was introduced? I found out a few days ago that my yosys compiled from about 1.5 months ago doesn't have it
<daveshah>
It was about this time last year
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<cr1901_modern>
... huh. I wonder why mine doesn't have it (answer: b/c Windoze, but I should still check/fix it)
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<porglezomp>
Hey, are attribute names decorated somehow? Like do they get the \ or $ prefixes?
<cr1901_modern>
They shouldn't be... I have an example of JSON output, lemme check
<porglezomp>
Oh, it looks like they might internally. Let's see what the ID() macro does
<cr1901_modern>
Oh, internally... I don't know :(
<porglezomp>
Looks like it
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<cr1901_modern>
Well interesting... TIL
* cr1901_modern
feels like he's been saying "I don't know" a lot lately
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<ZirconiumX>
porglezomp: I think you're actually looking for NEW_ID instead of ID.
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<emily>
fantastic naming
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<porglezomp>
ZirconiumX: In this case, I need ID for indexing into the attributes map.
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<mwk>
hi, I'm looking for some brave soul who knows EDIF
<tnt>
mwk: does "keep" really have to keep the net name ? I thought that net just had to exist physically but not necessarely have the verilog signal name ...
<mwk>
well, the point is usually to refer to that net in eg. a constraint
<ZirconiumX>
To be honest the way *I* would satisfy it is that since A and B are aliased you can pick one and still have the node without the multiple driver problem
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<strubi>
I
<strubi>
Would the 'keep' keyword just prevent the wire from being optimized away?
<strubi>
Wouldn't.
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<ZirconiumX>
The problem is that the wires are aliased
<strubi>
Sounds like a clash to me then..but I only know the VHDL side
<strubi>
while at identifiers: Anyone debugging using GTKwave? I see funny things when not using public names (like "$gnagna")
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<porglezomp>
What's the recommended way to distribute extensions? As a hack I'm installing them into a directory under the yosys data dir so that it can find its files with +/<extension>/<stuff> paths. Is that fine?
<cr1901_modern>
The honest answer in my experience is that "most ppl don't actually make yosys plugins and just hack directly on yosys". But at least the above two plugins seems to be consistent in install procedure
<porglezomp>
Ok, nice, just need a slightly deeper subdir.
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<porglezomp>
Ah nice, now I can just do yosys -m nangate and things work!
<cr1901_modern>
great :D!
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<porglezomp>
Anyone who's used nextpnr: should "Running main analytical placer" be taking a really long time with no progress indicators?
<porglezomp>
I haven't had anything printed since that showed up in the past 20 minutes
<mwk>
it should have progress indicators
<mwk>
it can take some time, but not more than a minute I think?
<mwk>
it does one status line per (iteration, cell/bel type) combo