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<corecode>
how do you cast constants to a specific width? like assign foo = WIDTH'(4);
<whitequark>
in verilog or SV?
<ravenexp>
I use "localparam [WIDTH-1:0] a = 4;"
<corecode>
in open source yosys
<tnt>
4'd4
<tnt>
oh wait, nm
<tnt>
I think I just do assign foo = 4;
<corecode>
ok, the example might be not so useful
<corecode>
say assign foo = {some_val, WIDTH'(0)};
<corecode>
meh, 0 is also not so good, because you could use a repeat
<corecode>
i hope you understand what i mean
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<tnt>
is some_val a signal ?
<corecode>
yea
<corecode>
but it's about constants that need to be sized to a param width
<tnt>
that just doesn't exist
<tnt>
so you need to work around it ...
<corecode>
:)
<corecode>
okay
<corecode>
it's a sv thing
<corecode>
but yea
<tnt>
Is it even in SV ?
<corecode>
i was asked in another channel
<corecode>
allegedly
<corecode>
icarus suppors it
<tnt>
Ah yeah indeed. But yosys definitely doesn't even with the -sv switch. I didn't know that.
<tnt>
For the case you posted above I usually work around it by assigning parts of 'foo' independently. Like assign foo[WIDTH-1:0] = 1234; assign foo[TOTAL_WIDTH-1:WIDTH] = some_val;
<corecode>
yea the sv bnf shows that a ' cast can be a simple_type, which in turn can be a ps_parameter_identifier
<tnt>
I find that using SV features is hit and miss :/ I really only like to use what works in all of yosys/iverilog/verilator ... that means basically not much.
<corecode>
yea
<corecode>
thanks
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<daveshah>
mwk: can you mark IOBUFDS IOB as `(* iopad_external_pin *)`? I don't have ISE set up so can't rerun cells_xtra.py and don't want stuff to get out of sync if I manually change
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<mwk>
... huh? I seem to recall I already merged that fix
<daveshah>
lambda: the problem is that ddr3_dq and ddr3_dqs need to be inout not output
<daveshah>
manually fixing it in the JSON gets past packing at least
<daveshah>
of course it should fail more gracefully than it does, I will take a look when I have a moment
<daveshah>
I can't get past placement as there seem to be too many PLLs
<lambda>
daveshah: huh, that's gotta be a ghdlsynth bug then - they're declared inout throughout the entire design. I'll look into that
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<daveshah>
It's also possible it's a Yosys issue in deminout
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<lambda>
regarding too many PLLs: litedram uses two (though I think that might be possible to trim down to one), and my design uses another one, while xc7a35t should have 5 total, right?
<daveshah>
It's possible x-ray doesn't support all of them, or didn't when I wrote the export tool
<lambda>
I think nextpnr has shown both 2 and 5 in the past, might be misremembering though
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<lambda>
daveshah: the inout thing seems to be on ghdlsynth, 'write_verilog' already shows inouts as outputs.
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<tnt>
ZirconiumX: maybe we should move here :p
<tnt>
Quick test on my small soc shows 2000 -> 2500 LCs with flow map and seems slower as well (although there is really very few failing path)
<ZirconiumX>
I said it was experimental, not better :P