clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> daveshah: I want to enter Yosys into a codegolf.se challenge now.
<daveshah> Challenge: achieve Verilog reflection by using DPI-C to access Yosys' memory
<corecode> explain
<corecode> i understand 10%
<corecode> aaah
<corecode> plugin
<ZirconiumX> corecode: Yosys supports FFI through DPI-C, which lets you do effectively arbitrary code execution.
<ZirconiumX> In this case Dave suggested using it to read Yosys' memory and perform reflection
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<ZirconiumX> What would cause a "Multiple edge-sensitive events found for this signal" error from Yosys?
<mwk> too many posedge * in sensitivity list
<ZirconiumX> This is coming from nMigen, so it's a bit tricky to check
<mwk> still
<mwk> it happens in proc_dff pass for a process that has more than one edge trigger
<mwk> (asynchronous resets are handled in an earlier pass, proc_arst)
<mwk> so you'd need to dump the rtlil from nmigen and look for funky processes
<mwk> it could be a result of a botched async reset
<ZirconiumX> Wonderful.
<tnt> does nmigen even have async reset ?
<ZirconiumX> It has a full reset network by default
<tnt> yeah. Sync reset.
<tnt> (AFAIU)
<ZirconiumX> Mm. Not sure then.
<tnt> Digging a bit, looks like it does support async reset, but the default is still sync.
<tnt> from what I read it was omigen that didn't do async without tricks.
<whitequark> yep
<whitequark> that was one of the problems I set out to fix with nmigen
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