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<twnqx>
is there a rule of thumb at which point a design becomes too large to be placed, or is that too varying?
<daveshah>
In general <90% should be OK
<daveshah>
Above that it can become marginal but that depends on the specifics of the design
<twnqx>
i am at 81% (312/384) and nextpnr fails (lp384) :(
<daveshah>
On the iCE40 I've seen designs at 98% place and route fine
<daveshah>
Do you have a lot of different set/reset/ce signals?
<twnqx>
hm, i'd be tempted to say "no", but i guess i'll have to think about that
<daveshah>
You can try the Yosys option -dffe_min_ce_use 4
<daveshah>
or -dffe_min_ce_use 8
<daveshah>
to synth_ice40
<twnqx>
fun, even 2 makes it work
<twnqx>
thank you!
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<az0re>
In Makefile, is `msys2-64` the MinGW 64 bit compiler?
<az0re>
Looks like it
<az0re>
I'm having trouble building on Windows in cygwin, `msys2-64` config, tcl-dev is installed in Cygwin setup
<az0re>
I get: "./kernel/yosys.h:81:12: fatal error: tcl.h: No such file or directory"
<az0re>
Despite tcl.h existing in /usr/include/
<az0re>
I wonder if the build config is missing some that include directory somehow?
<daveshah>
Is there any reason you need to use Cygwin and not msys2 itself?
<whitequark>
daveshah: i'm wondering if DFFEs can be legalized back in nextpnr
<whitequark>
to avoid having dffe_min_ce
<daveshah>
The problem is that if you want any kind of efficiency you need to re-pack the LUTs
<daveshah>
dffe_min_ce unmaps them before LUT mapping which is even more efficient
<whitequark>
yup
<daveshah>
I don't want to do LUT transforms in nextpnr yet
<whitequark>
it feels that maybe abc9 should be a part of nextpn... ahhh
<whitequark>
(not *literally* abc9)
<daveshah>
I have plans for a library that is a bit like that
<daveshah>
for retiming, physical resynthesis etc
<whitequark>
that sounds awesome
<daveshah>
but it could be a year off, don't get your hopes up
<daveshah>
I think by the time you start doing retiming it becomes needed
<whitequark>
yup, i understand that
<whitequark>
it does not sound like something that can be done in a few months, anyhow
<daveshah>
The first challenge is just designing a netlist structure that is efficient for these kind of transformations, without being restrictive as abc's
<ZirconiumX>
I mean, for what it is, ABC is quite efficient
<ZirconiumX>
Just, lacking a lot of important metadata it seems
<daveshah>
Yes, although I want first-class whitebox support
<daveshah>
it may be that AIGs aren't a bad way of representing the contents of boxes
<daveshah>
but it's finding efficient ways of tracking things like attributes and source tags that's half the problem
<whitequark>
what are the reasons to prefer AIGs or LUTs for whitebox contents?
<daveshah>
Imagine a DSP whitebox
<whitequark>
oh, point.
<daveshah>
If you represent the whole whitebox as one LUT that is quite big
<daveshah>
You could use a graph of LUTs, but at that point an AIG is probably just as good
<ZirconiumX>
From what I was reading on how FRAIG works, ABC has a library of precomputed optimal AIG for up to 20-inputs
<ZirconiumX>
Which is a mildly terrifying thought, but
<az0re>
daveshah: Not *need*, I guess, but I prefer it if I must use Windows. Anyway I just want to test something.
<daveshah>
az0re: I don't know if anyone compiles Yosys in Cygwin often, but msys2 should be a better trodden path
<az0re>
I see now, though, that there is an explicit cygwin config
<az0re>
What exactly is msys2, anyway?
* az0re
is not a Windows user
<daveshah>
As far as I know, msys2 is more of a gnu-style build environment in Windows than a build and runtime environment like Cygwin
<daveshah>
I haven't done much Windows stuff for a few years either
<daveshah>
so might not be quite correct here
<whitequark>
cygwin provides a POSIX environment to the compiler, the build system, and the application. msys2 provides a POSIX environment to just the compiler and build system
<whitequark>
i.e. cygwin builds produce cygwin-dependent binaries that think they run on a POSIX platform. msys2 builds produce native Windows binaries
<az0re>
I see, thanks. And how do I compile Yosys with MSVC?
<az0re>
Is it supported at all? I recall seeing `#if defined(__MSVC)` or similar in the code base
<ZirconiumX>
(I need this because Quartus takes RAM init as a hexadecimal string)
<daveshah>
You use double quotes even for single characters in Verilog
<ZirconiumX>
Oh, right, okay
<twnqx>
and now to understand what the fpga actually does after the changes, correct it do useful and adopt the controller code \o/
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<Sarayan>
Ok, I have a RTLIL::SigSpec, and I want to make a new SigSpec that extract a bit of it, can I do that?
<mwk>
a single bit?
<mwk>
just spec[i]
<mwk>
I mean, that gets you a SigBit, but that's perfectly assignable to a SigSpec
<Sarayan>
cool, thanks
<Sarayan>
and a bit range while I'm at it?
<mwk>
spec.extract(offset, length)
<mwk>
this gives you a new SigSpec
<Sarayan>
excellent, thanks
<whitequark>
ZirconiumX: have you seen how strings work in verilog? it's so cursed
<whitequark>
a n-character string is just a (n+1)*8 bit constant literal
<ZirconiumX>
I have, yes
<ZirconiumX>
And I need to manipulate strings in verilog to initialise LUTRAM, whitequark
<ZirconiumX>
Because Altera fucking hate me I think.
<whitequark>
right
<ZirconiumX>
So after getting quite annoyed trying to do it myself, I'm going to see what Quartus does and then copy them
<Sarayan>
wq: You mean like in C? ;-)
<mwk>
Sarayan: it's nothing like C...
<whitequark>
it's very slightly like C?
<Sarayan>
yeah, it's bits and not bytes
<whitequark>
the difference is that verilog doesn't have bytes or pointer decay
<Sarayan>
yeah, verilog is decay
<mwk>
I mean, for one, C has types
<mwk>
it's not a high standard, C types, but it is one that Verilog fails to meet
<Sarayan>
what's the difference between $logic_not and $not?
<mwk>
$not is per bit, ie. ~signal
<whitequark>
Sarayan: have you looked at cxxrtl.h yet?
<mwk>
$logic_not is ~signal
<mwk>
err
<mwk>
$logic_not is !signal
<whitequark>
it has C++ implementations of many cells, which may be helpful
<mwk>
ie. it's 1 if all the signal bits are 0
<Sarayan>
wq: No, I only use it
<Sarayan>
nwk: Ah I see, thanks
<Sarayan>
verilog has ! ?
<mwk>
... how do people keep making that typo
<mwk>
yes, it does
<Sarayan>
if (!rstn)
<Sarayan>
cnt <= 0;
<Sarayan>
I guess that's a logic-not, whatever the width of rstn
<mwk>
yes
<Sarayan>
ok, good
<mwk>
it's equivalent to $not for single-bit signals, of course
<Sarayan>
yeah
<Sarayan>
which is why I wasn't seeing the difference
<Sarayan>
if my example had been n:1, It's have guessed I think :-)
<Sarayan>
I like the idea of integrating slang given I don't know verilog or rtlil :-)
<Sarayan>
funniest thing is it's kinda going somewhere
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<ZirconiumX>
daveshah: Does the Xilinx firmware.hex still count primes?
<ZirconiumX>
Or is it just counting up?
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<Sarayan>
In verilog, can you have expression statements that are not assign?
<ZirconiumX>
"expression statements"?
<Sarayan>
well, that a laguage grammar term, but that all expressions that are use in place of a statement
<Sarayan>
e.g. in C you can write 'x++;' which is an expression turned into a statement
<Sarayan>
you can even write 'x;' but that does nothing
<whitequark>
do you mean within processes?
<Sarayan>
and subroutine calls are expressions in C
<Sarayan>
yeah
<whitequark>
i think you can have at least a=b, a<=b, fn(a)
<whitequark>
actually i'm not sure if "a=b" is an expression in verilog
<whitequark>
i thought it was only a statement?
<daveshah>
SystemVerilog has ++
<daveshah>
I think it is only valid inside always blocks or a few other places like that
<daveshah>
I don't know if it is a statement or expression though
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<Sarayan>
I think slang has it as expression
<Sarayan>
so I should expect more than just <=
<Sarayan>
oh, it has calls as expressions too, so yeah
<Sarayan>
also, in rtlil, where is assign hiding?
<daveshah>
module->connections_
<Sarayan>
even the conditional ones?
<whitequark>
those are in processes
<Sarayan>
RTLIL::Process doesn't have much of an interface
<Sarayan>
looks like you're supposed to hit RTLIL::Module::processes directly
<whitequark>
daveshah: i suspect your SNES thing might be suffering from #1944; can you check at -O2 or even -O0?
<daveshah>
What difference should I expect to see?
<whitequark>
you had corrupted memory, right?
<daveshah>
No, that was just a typo on my part
<whitequark>
ahhh ok
<daveshah>
after fixing that it all appears to work fine
<whitequark>
sweet
<whitequark>
how many fps? :D
<daveshah>
Not far off 1fps
<whitequark>
hm, that's not that bad
<whitequark>
daveshah: so here's one theory i'd be interested to test but so far have been unable to
<daveshah>
no, I miscounted, in the proper working one it is about 0.2fps
<daveshah>
12fpm
<whitequark>
the theory is that cxxrtl simulation can get faster by exploiting the nature of input verilog, specifically, by translating processes to if/elif statements and just never computing results it doesn't need
<whitequark>
rather than throwing them aay
<whitequark>
the problem is that flatten chokes on processes
<whitequark>
and on non-flattened designs it makes no difference
<daveshah>
In this case, that wouldn't help as ghdl doesn't create processes afaik
<whitequark>
oh
<daveshah>
I think it only creates DFFs and I don't think there's any way to change that
<whitequark>
ok, i see
<whitequark>
if you see any inefficiencies in the generated c++ i'm all ears
<whitequark>
(that can be fixed)
<daveshah>
Something I would like is reading memory init from a file, but that depends on the $meminit cell
<daveshah>
*$memfileinit
<daveshah>
or whatever the file variant would be called
<whitequark>
will happily add this if you add the cell
<whitequark>
it would be also interesting to have some way to say "the contents of this memory is a placeholder called X"
<daveshah>
Yeah, I'll think about that
<whitequark>
sweet :)
<daveshah>
It would be nice to easily do those kind of changes post-PnR in a cleaner way than icebram etc
<whitequark>
yes, exactly what's that for
<whitequark>
and in cxxrtl i can just call a user function
<mwk>
... have been thinking the same thing for a while
<mwk>
something like passing "relocation" attributes along with the blockrams / lutrams / lut roms
<mwk>
"insert file abc.bin bits 1234-1337 here"
<mwk>
probably with some crazy permutation / bit slicing support
<mwk>
to support all the crazy shit that happens to memories as they get lowered
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<ZirconiumX>
mwk: ironically that would probably be what I need
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<whitequark>
daveshah: oh btw you can just write the entire memory at startup
<daveshah>
Oh, that seems like a good option for now
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<whitequark>
I should add an overload for that case
<whitequark>
or maybe just poke into `top.p_memory.data` directly
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<whitequark>
that actually seems like the most reasonable solution for your case
<whitequark>
oh, `top.p_memory[index]` should work just as well
<whitequark>
I forgot I added that
<Sarayan>
there's an easy direct access to memory?
<Sarayan>
I've had to implement cpu write to fill it from c++ for now :-)
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<whitequark>
syre
<whitequark>
*sure
<whitequark>
you can do `top.p_memory[0] = value<32> {123u};`
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<tpb>
Title: cxxrtl: minor documentation and usability improvements by whitequark · Pull Request #1947 · YosysHQ/yosys · GitHub (at github.com)
<whitequark>
this removes const from ROMs so you can update them
<ZirconiumX>
Is there a way to see what memory_bram picks as init value for a memory?
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<whitequark>
which cell or which value?
<ZirconiumX>
Value
<ZirconiumX>
I kinda added a hack for it
<ZirconiumX>
So I can see if the LUTRAM values make sense
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<ZirconiumX>
Y'know, if memory_bram knows it's emitting a ROM (which it can tell by there being zero write ports), and it can tell that an initialiser is a constant value (which it can through initparam) it makes next to no sense for it to be emitting zero-initialised ROMs
<ZirconiumX>
Instead of constant drivers
<twnqx>
these weird errors creep me out. i switch two values in an emulated ROM, and suddenly my design doesn't fit any more.
<ZirconiumX>
twnqx: "emulated ROM"?
<ZirconiumX>
The case statements?
<twnqx>
a case statement on a 3 bit address range, yes
<ZirconiumX>
And how many other variables do you use in that case statement?
<twnqx>
noen
<twnqx>
none
<ZirconiumX>
To be fair, consider that ABC - the synthesis engine in Yosys - is heuristic, and subtle changes can cascade into major differences
<twnqx>
however, i know something else is broken, i just can't find it yet
<twnqx>
because one address is never reached, even though it comes from a counter.
<Sarayan>
counter reset issue, or it's full range?
<twnqx>
the reset comes from the ROM, my bet is on insufficient sync (too much logic, not enough regs)
<twnqx>
hm, nearly any change too the "ROM" makes it not fit
<twnqx>
and the reset is synchronized even
<twnqx>
what does yosys consider a "dead case" for removal? if i have a decode of 2'b0?, 2'10, 2'b11, is there a dead case?
<Vinalon>
Speaking of how 'simplifying' logic can sometimes lead to larger and slower designs, does the ABC algorithm have any sort of 'seed' value that you can manually change?
<twnqx>
hm... what does "number of cells" in yosys output mean?
<twnqx>
if yosys claims 384 cells are needed in an lp384, nextpnr might not be right with 82% utilization...
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<daveshah>
That's total cells of all varieties, some of those will pack together
<Vinalon>
the timing analysis lists the actual utilization once the design is packed under "Device utilisation:"
<twnqx>
well, my deisgn is unplaceable
<Vinalon>
it still might show up; I have a design that's showing "ICESTORM_LC: 6755/ 5280 127%" right now :P
<ZirconiumX>
twnqx: You can fit a LUT4 and a DFF together in an LC, but Yosys counts these as separate.
<twnqx>
both variants are at 82%, one is mapable, one is not :/
<twnqx>
and in the mapable, one step is not reached
<twnqx>
aaand now it is, ok
<twnqx>
and now it's not again
<twnqx>
wow
<twnqx>
i really must be bad at this
<Vinalon>
as someone who is also still learning about digital design, the tooling can seem sort of opaque sometimes - don't worry if it doesn't feel intuitive
<Vinalon>
also, I don't think the lp384 has any RAM resources; maybe that complicates memories a little bit?
<whitequark>
as someone who maintains a HDL, it is frankly not much easier for me to figure out where the heck the resources went
<twnqx>
i have no real memories - just a few counters, buffers, shift registers
<whitequark>
twnqx: you're not bad at it. the tools are. i even wrote a pass that should somewhat solve this problem, though it's not yet in a state where it'd help you
<twnqx>
whitequark: the version that compiles changes behavior between different runs. that means i somewhere made a mistake, assuming the tooling isn't broken
<twnqx>
differenr runs = different compile runs
<whitequark>
twnqx: philosophically, if the tools don't help you make deterministic designs, they are, in some ways, broken...
<whitequark>
but more concretely
<whitequark>
is it a fully synchronous design? no generated clocks? only one `posedge x`?
<whitequark>
*only one `x` for every `posedge x` you use?
<whitequark>
are the external inputs resynchronized to the clock?
<twnqx>
the parts with two @posedge X are the only ones working reliably (SPI interface), and there are no other inputs, just clock and outputs
<whitequark>
is the difference in behavor something you observe when using SPI, or is SPI totally unused?
<lambda>
hmm, `opt_muxtree` isn't turning (a ? x : (b ? x : (c ? x : (d ? x : y)))) (four 80-bit muxes) into (a || b || c || d ? x : y) (one 80-bit mux and a cheap or-reduce) - isn't that what it's supposed to do though?
<ZirconiumX>
lambda: no, it's not
<twnqx>
actually, thank you for this pointer... i might be having an issue with an asynchronous reset, though i wonder how i would handle a "load register with value froom shiftregister on CS going high, set to 0 on something internally" without "@(posegde X or posedge reset)"
<ZirconiumX>
lambda: "This pass analyzes the control signals for the multiplexer trees in the design and identifies inputs that can never be active. It then removes this dead branches from the multiplexer trees."
<lambda>
ZirconiumX: oh, right, I misread the manual. is there a pass that should do this then?
<whitequark>
twnqx: is the SPI clock much slower than the FPGA clock?
<twnqx>
uhhhh and THAT asynchronous signal is not buffered
<twnqx>
simple as that, that's the nondeterministic part
<twnqx>
(the reset)
<ZirconiumX>
lambda: at present, I don't think so, but whitequark has/had opt_match that I *think* would have detected this
<whitequark>
ZirconiumX: actually you just gave me a great idea
<ZirconiumX>
*proc_match
<lambda>
well, let's hope ABC takes care of it during synthesis
<twnqx>
thanks again whitequark!
<whitequark>
ZirconiumX: the pass is called proc_match, but what if... it was called opt_match?
<ZirconiumX>
<obnoxious Shakespeare quote about "what's in a rose">
<whitequark>
ZirconiumX: i had the most problems with the part where it translated processes to muxes. what if i just ditch that, and instead make it optimize match order of bits in processes alone?
<ZirconiumX>
I mean, I saw it as an optimisation pass
<ZirconiumX>
But sure
<whitequark>
it was combined optimization plus codegen pass
<whitequark>
but I think I can extract just the optimization part into a much much smaller pass
<whitequark>
in fact, I now see I can break it up into at least three different passes
<ZirconiumX>
You're welcome?
<ZirconiumX>
^^;
<whitequark>
ZirconiumX: thank you. your typo was incredibly helpful actually
<twnqx>
and that one extra flip flop doesn't fit any more *cries*
<ZirconiumX>
whitequark: I suppose sometimes it just takes that tiny thing to make things click
<lambda>
twnqx: just stick an external 74xx flip-flop on the board :)
<twnqx>
:P
<twnqx>
too bad lattice doesn't make larger LP devices in the QFN casings
<twnqx>
LP1K in QFN32 or so would be nice
<ZirconiumX>
Now for another whitequark hug of Twitter notifications (I don't mind, it's just funny)
* twnqx
reduces camera trigger length to ~10µs and reduces the 6 bit counter to 1 bit
<twnqx>
design fits.
<twnqx>
noidea if camera still works, though...
<lambda>
twnqx: oh, high speed cameras? (sorry, your nick doesn't ring any bells here)
<twnqx>
no, not really, but external trigger
<twnqx>
theoratically 160fps tops
<lambda>
ah, neat
<twnqx>
sadly the jetson nano connected to it can only process 20fps :P
<twnqx>
also global shutter to not cause issues with PWM dimmed LED lighting... and the fpga controlls all of that (LED sequence, PWM dimming, camera trigger)
<lambda>
I was wondering what the precise shutter control was about, that makes sense
<ZirconiumX>
twnqx: You're doing all of that in an LP384, and I'm eating up a HX8K just to generate chess moves
<twnqx>
heh, it's just a bunch of counters and a shiftregister that can load some paramaters
<ZirconiumX>
I, uh, use quite a lot more than that
<twnqx>
back in university i did image processing on a... virtex 2 i think, that was also a bit more
<lambda>
good news: synth_ice40 manages to figure out those mux chains and uses the same amount of LUTs as with only one mux in the RTLIL
<twnqx>
my size problems really started when i needed a third 24bit brightness set and a one-of-three mux...
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<twnqx>
*sigh* now nextpnr fails with 78% device utilization
<twnqx>
daveshah: following your suggestion of -dffe_min_ce_use 8 causes "Warning: Wire top.spislave.cmd has an unprocessed 'init' attribute." (unlike e.g. 4, which keeps the design unplaceable) - is that critical?
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<ZirconiumX>
twnqx: Yes; I treat a similar situation in synth_intel_alm as a hard error
<ZirconiumX>
It means Yosys was unable to implement a flop in logic
<ZirconiumX>
Or, well, emulate specific flop semantics
<mwk>
it means some register initial value was ignored due to being unimplementable
<mwk>
it could either be due to a FF type not supported in hardware (say some targets cannot support a ff with async set and initial value of 0), or due to an initial value attached to something where it doesn't make much sense in the first place
<mwk>
are you using FFs with async set/reset?
<daveshah>
It sounds more like a bug in dffe_min_ce_use
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<twnqx>
well, in my particular case i'll just don't care... i am trying to init it to 0 anyway
<twnqx>
mwk: and yes, one bit of this has an async reset
<mwk>
reset or set?
<twnqx>
reset
<mwk>
that should work
<twnqx>
it throws no warning in yosys until i go to -dffe_min_ce_use 8, but with less than that nextpnt can't route it
<twnqx>
and i am really a bit stumped as i am now below 80% utilization in nextpnr
<daveshah>
Place, or route?
<twnqx>
"ERROR: Unable to find legal placement for all cells, design is probably at utilisation limit."
<twnqx>
so, place
<daveshah>
Can you try with --placer sa as a nextpnr argument?
<daveshah>
Sometimes I think SA does slightly better at designs on the margins of placement
<twnqx>
that works....
<twnqx>
that even works without any --dffe_min_ce_use
<daveshah>
Oh, that's interesting, I think there is definitely room for improvement in HeAP there then