<FFY00>
waiting for my ecp5 board to be able to test
<daveshah>
I don't know how much work it would be to get that into a host and to get a Linux driver working
<rjeli>
i don't mind writing the gateware for the driver
<daveshah>
What bandwidth do you need?
<rjeli>
no more than 1mbps
<daveshah>
An ESP32 would probably be much easier to interface
<rjeli>
are the pcie to uart bridges that come up on google real?
<daveshah>
Or any of the other WiFi+SoC chips as a bridge
<rjeli>
yeah, that's my next option but esp32 has blobs
<daveshah>
Are you sure the ath9k is blob free?
<rjeli>
and not the niceties of ath9k
<rjeli>
yeah, there's no cpu on it, no firmware
<rjeli>
for a reasonable definition of cpu ofc
<FFY00>
which also makes it harder to interface with :)
<daveshah>
It could easily have firmware in ROM
<daveshah>
Which is much worse than an exposed binary blob imo
<rjeli>
ok sorry i'm unclear, i am not so concerned about the foss anti blob side as I am the low level rf control that ath9k exposes
<daveshah>
Ahhh I see
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<rjeli>
the esp32, or rtl chip, or any of the wifi module SoCs have very limited configuration
<daveshah>
What about just getting a frontend, ADC and DAC and doing 802.11 in gateware :)
<rjeli>
:)))
<ronyrus>
hi all. I'm trying to instansiate Pseudo-Dual Port RAM Primitive (PDPW16KD) in ECP5 and I'm kinda lost. When looking in the Lattice Memory guide I see the "Write Enable" signal described in the table, but it seems that it's absent in yosys.
<ronyrus>
Am I doing something wrong or stupid? I'm pretty new here, but sounds like write enable is pretty important ...
<daveshah>
Oops, seems that was left off
<daveshah>
When Yosys infers it it just uses the byte enables
<daveshah>
I'll look into fixing
<ronyrus>
thanks a lot!
<daveshah>
For now just using the byte enable signals should be a workaround
<ronyrus>
byte enable would assert the write enable?
<daveshah>
I think the write enable defaults high in pnr
<ronyrus>
ah
<daveshah>
So the byte enable is enough
<ronyrus>
cool
<daveshah>
Hmm, I can't see a write enable in the Lattice synthesis primitive definition either
<ronyrus>
yeah, that's a bit weird. some documents contain it, other do not.
<daveshah>
I think it is "write clock enable" (CEW) which Yosys has too
<ronyrus>
ok
<ronyrus>
btw, speaking of byte enables in the ECP5 EBR. I see it's being mapped into lower bits of the address lines, but I don't understand why. I thought that the address is expressed in words with the width that was set by a parameter.
<daveshah>
I don't understand why either, it is just Lattice reusing signals afaics
<ronyrus>
so, the actual address lines should be shifted?
<daveshah>
Yes, they are effectively left-aligned in the wider modes
<daveshah>
address bit 13 is always the MSB
<ronyrus>
interesting
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<ronyrus>
heh, they are also splitting the data if you want to use 8 bits and not 9...
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