clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<chipb> ZirconiumX: lack of ram init? do xilinx families feature memory init for *all* types of embedded rams?
<ZirconiumX> chipb: AIUI Xilinx UltraRAM can't be initialised
<ZirconiumX> (in the UltraScale+ family)
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<mwk> it can be initialized to any value you want, as long as it's zero
<ZirconiumX> mwk: or is a permutation of zeroes!
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