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<tnt>
mwk: the up5k spram can't even be init to zero, content is random on start.
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<sensille>
can i tell yosys to complain about uninitialized registers?
<sensille>
or to assume them as zero?
<tnt>
if you care about its initial value you should have a reset on it.
<sensille>
in case of fpgas, isn't the initial value part of the bitstream? or at least fixed as 0?
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<daveshah>
Which FPGA?
<sensille>
ecp5 in my case
<daveshah>
then the initial value is the same as the reset value
<daveshah>
defaulting to 0 if there is no reset and no init
<daveshah>
note that there are a few places where a sync reset may be inferred even if there isn't an obvious reset in the design
<sensille>
i just want yosys to warn me in case i forget an initial value
<daveshah>
(e.g. q <= sel ? 1'b1 : d) would infer a sync set and therefore q would default to one-initialised
<tnt>
sensille: sure but for instance if you're using a PLL you should hold all your logic in reset until it locks because until then the clock can do whatever ...
<daveshah>
I don't think there's a way to do that
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<sensille>
unfortunately verilator doesn't handle uninitialzed values well, either
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<keith-man>
This might sound weird, but fun I was think of trying to use yosys to synthesize with discrete gates. I can see that it can accept liberty files, but when searching for how to write one it seems like they can be quite complicated. When I all I wanted to do was mainly have delay, rise and fall times, and pin capacitance area. Just to try something
<keith-man>
out quickly.
<keith-man>
Also when looking I see that abc can use a genlib file which seems simpler.
<keith-man>
would perhaphs better to generate a bliff from a Verilog file and then use abc directly?
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<ZirconiumX>
Ugh, they're gone
<mwk>
well, it's a publicly logged channel, you can just answer into the aether
<Sarayan>
beware, the abyss^Waether may answer back
<keith-man>
I guess I'll just have to experiment once I am less sleepy. It's really early in the morning for me I should probably sleep.
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<ross_s>
Has anyone seen the error 'Failed to find a route for arc 125 of net $PACKER_GND_NET'? Attempting to synthesize a 36 bit mult on the ECP5, using a clarity designer generated file consisting of 4 direct mult18x18ds and two alu54bs
<daveshah>
The ALU54B isn't fully working yet
<ross_s>
is there anything a layperson can do to help out?
<daveshah>
In particular there is nothing to correctly constrain the ALU54B and MULT18X18D together
<daveshah>
The most useful thing to do is put the design somewhere so I can have a look
<daveshah>
Particularly if it is something that can easily be tested on hardware
<daveshah>
Also, if you would be able to build it in Diamond and take a screenshot of the placement in physical view and provide the Diamond bitstream, that would also make it much quicker for me to finish
<ross_s>
ought to be - I've been trying to work out how the pipeline stuff works (since default inferred 18x18 is a bit slow), so I just have a test case that exposes a shift interface to the mult
<ross_s>
ok; I'll get the test code up somewhere and work on the diamond stuff
<ross_s>
running make will generate the error I mentioned above
<ross_s>
and I have now just pushed a commit that adds a diamond-generated bitstream to that repo
<daveshah>
Thanks!
<ross_s>
oops just remembered you wanted a screenshot of the physical view as well
<ross_s>
that's in there as well now
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<ross_s>
Related to previous discussion, does anyone know of a better DSP documentation resource than TN1267?
<ross_s>
Through trial and error I've verified that .REG_OUTPUT_CLK("CLK0") adds once cycle latency, and similarly setting REG_INPUT{A,B}_{CLK,CE,RST} adds a second one, but .REG_PIPELINE_{RST,CE,CLK} doesn't appear to do anything? I can't find example timing diagrams anywhere.
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<ross_s>
Do the pipeline registers only take effect if the mult is chained into an alu perhaps?
<ross_s>
It also looks like the in/out register config on the mult block isn't accounted for in the nextpnr timing, I can make a PR for that along the same lines as https://github.com/YosysHQ/nextpnr/pull/423 if I'm correct in thinking that setting both .REG_INPUT{A,B}_CLK to a non-"NONE" value enables the in registers
<tpb>
Title: Add support for REGMODE to DP16KD by rschlaikjer · Pull Request #423 · YosysHQ/nextpnr · GitHub (at github.com)