clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ashfaq1717> how to convert NOR2 to NOR3 using techmap
<daveshah> Do you mean one NOR2 to one NOR3? Techmap isn't for combining cells
<tpb> Title: cxxrtl: add support for simple and templated C++ black boxes by whitequark · Pull Request #1963 · YosysHQ/yosys · GitHub (at github.com)
<ashfaq1717> i have replaced nor 3 to combinations of nor 2 similarly I want to do vice versa
<daveshah> extract is intended to be the opposite of techmap
<ashfaq1717> can you please write me the verilog code for extract map nor2 nor3
<ashfaq1717> can I put this on github?
<ashfaq1717> module NOR3X1(input A, B, C, output Y);wire first_output;NOR2X1 first(.A(A), .B(B), .Y(first_output));NOR2X1 second(.A(first_output), .B(C), .Y(Y));endmodule
<ashfaq1717> this was nor3 to nor , I want a code for nor2 to nore3
<daveshah> What happens when you do extract with that file?
<ashfaq1717> I don't know exact syntax how I connect signals of nor2 to nor3 as I done for the above, I want a file which can do this using extract or techmap
<ashfaq1717> can I extract with the same file?
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<ZirconiumX> ashfaq1717: that's what daveshah is asking you to do
<ZirconiumX> Besides, couldn't you at least thank me for that code?
<ZirconiumX> Congrats, whitequark
<whitequark> thnks!
<ashfaq1717> when I use extract map with the above file it says 0 matches found it means we can't extract with the same file
<ashfaq1717> thank u ZirconiumX but I couldn't understand your code
<ZirconiumX> ashfaq1717: how come? You literally straight-up copied it
<tpb> Title: How to convert one cell to a combination of other cells? · Issue #1891 · YosysHQ/yosys · GitHub (at github.com)
<ashfaq1717> brother its Ok, it replaces the cells nor3 to nor2 I have checked it, but doing vice versa with extract it dosn't replace nor2s to nor 3
* ZirconiumX sighs in being non-binary
<ashfaq1717> any solution?
<ZirconiumX> I've never used extract because I've never needed to use extract
<ashfaq1717> its Ok. any one else?
<ZirconiumX> The thing is, by the time you need to use extract it is too late to do the thing you want to, generally
<ZirconiumX> It's far better to use techmap to break high-level things down into what you want, than to use extract to build up into what you want
<ashfaq1717> can you give me a example
<ZirconiumX> Say you want to make a specific adder
<ZirconiumX> It's best to try mapping either $add or ideally $alu to build the adder out of the cells you want
<ZirconiumX> Rather than try to build an adder from extracting half and full adders
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<ashfaq1717> how to convert DFFSR to DFF_P or DFF_N? what are benifits of doing so while Yosys automatically map to DFFSR?
<ZirconiumX> ashfaq1717: dffsr2dff
<ashfaq1717> yup
<daveshah> That's been removed
<ZirconiumX> And the benefits are that the DFF cells are simpler, use less area and need less routing.
<daveshah> opt_rmdff does everything it did
<ZirconiumX> Since I'm on my phone I don't have access to the latest docs, and Claire's only get regenerated when there's a major release
<ashfaq1717> from where can i get dffsr2dff file
<ZirconiumX> ashfaq1717: since opt_rmdff replaces it, use opt_rmdff instead
<ashfaq1717> ok
<ZirconiumX> Which is probably run by default, actually
<mwk> whitequark: that isn't the pull request that you needed stable avail_parameters order for, right?
<whitequark> mwk: nope, turns out i didn't need it after all
<mwk> ok, fair enough :)
<ashfaq1717> please refer me dffsr2dff file I want to see the difference by using it
<mwk> ashfaq1717: just dig it out from git, it was removed in https://github.com/YosysHQ/yosys/commit/38a0c30d65584335fee3e17f9075711853638ac3
<tpb> Title: Get rid of dffsr2dff. · YosysHQ/yosys@38a0c30 · GitHub (at github.com)
<ashfaq1717> hmm
<mwk> but it really is just a subset of opt_rmdff
<mwk> doing the same transform, but badly
<ashfaq1717> i synthesis a simple alu, run yosys script after abc , i use extract map to replace gate cells with a macro add cell but same result found no match as for nor3 previously,
<lambda> ashfaq1717: why do you want to do that though?
<ashfaq1717> I want to create an example how can I reduce the area by replacing many cells with a macro cell
<ashfaq1717> i am unable to synthesis a design to split it in gate cells and then map these cells to a macro cell
<ashfaq1717> kindly refer me some xample
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