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<az0re>
Can someone explain when exactly I should use `log_push()` and `log_pop()`?
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<ZirconiumX>
az0re: when you want passes to be counted as substeps in the log
<ZirconiumX>
Instead of 1. A; 2. B; 3. C; 4. D
<ZirconiumX>
You get 1. A; 1.1: B; 1.2: C; 1.3: D
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<lambda>
why is signed arithmetic in verilog such a giant pain again? from what I can tell, I only really have a chance of anything working if I first assign every input to a wire of width max(A, B, Y), then do the math, then assign it back to the output
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<ZirconiumX>
lambda: I think that's about what nMigen does
<ZirconiumX>
whitequark: ^
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<az0re>
ZirconiumX: Thanks.
<az0re>
But how does that interplay with log_cmd_error?
<az0re>
It just pops out of the whole stack?
<ZirconiumX>
Yep
<az0re>
Gotcha. Thanks.
<ZirconiumX>
az0re: log_cmd_error is unrecoverable (because there's a command syntax problem), so the stack doesn't mean much
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<lambda>
hm, truncating signed division is not easily optimized for power-of-two denominators (-3 / 4 = -0.75 = 0; simply shifting -3 right by 2 places gives -1 though). this is currently implemented wrong in opt_expr, too. I'm wondering, should it be replaced by a shift+add+reduce+mux or just not be optimized at all?
<whitequark>
i'm not really sure what kinds of practical designs use comb division in synthesis
<whitequark>
wait
<lambda>
FWIW the naive `x / (2^n) == x >> n` does hold true for all flooring divisions.
<whitequark>
are you talking about a constant denominator?
<lambda>
yes, constant power-of-two denominator, opt_expr.cc:1506 is wrong for signed division (working on fixing that)
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<whitequark>
i'd say optimize it, since division by power of 2 is one of the cases people do expect to work
<whitequark>
but it is a weak preference
<lambda>
alright, I'll see what I can do
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<tnt>
So, with cxxrtl, how would I generate a FST/LXT file containing all internal signals ?
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<ZirconiumX>
whitequark: ^
<whitequark>
tnt: right now, cxxrtl designs aren't introspectible at all beyond writing C++ code that accesses the registers
<whitequark>
i'll fix this though, i have a plan that will let you inspect even (most) comb wires in optimized designs without *either* slowdown when debug is not used, *or* any sort of <value optimized out> bullshit
<whitequark>
are you interested in *every* internal signal, even yosys $\d+ wires?
<whitequark>
or just all public regs? all public regs and wires? (in verilog terms)
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<tnt>
Really I just care about the 'wire/reg' that appear in my verilog code.
<tnt>
And I can do without 'memories' since those take a insane amount of space with little benefits in most cases.
<tnt>
Ideally if there is one I want traced I'd be able to mark it as such.
<whitequark>
tnt: what about... being able to request tracing any set of signals you want, at runtime, with no overhead if you aren't tracing any signals?
<whitequark>
(or memories for that matter)
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<whitequark>
(actually, i can emit delta compressed memories trivially, if the format supports them)
<tnt>
tbh, for me at least changing at runtime doesn't matter much. I just dump everything and inspect in gtkwave to find the issue. I wouldn't want to have to re-run the sim each time I want to inspect another module.
<whitequark>
ah i see
<whitequark>
the main benefit would be that you could have e.g. `--debug` as an option in your test code that activates such a mode
<whitequark>
and runs fast otherwise
<tnt>
yeah, that's definitely useful, run with 'file output' to do spot checks and if output is not as expected dive-in. And some way to include/exclude modules as well. Most testbench include way more than the DUT and I don't necessary need to trace all the support code.
<whitequark>
should be fairly easy. the main problem would be including/excluding modules in flattened designs. but solvable too.
<tnt>
well the signals should have some names based on hierarchy anyway so just some regexp match would be fine.
<whitequark>
urgh :S
<whitequark>
i mean sure i guess, something you could implement yourself
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<ZirconiumX>
whitequark: Is it feasible to use bugpoint to debug something other than Yosys?
<whitequark>
ZirconiumX: it hardcodes some yosys args at the moment
<whitequark>
but you could easily modify it, i think
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<ZirconiumX>
I'm currently trying to use creduce to debug a Quartus ICE, and I think bugpoint being RTL-aware is going to be much more efficient than creduce getting lucky
<whitequark>
sure, i think you could modify run_yosys
<whitequark>
be aware that bugpoint expects the synthesizer to be fast. it... is likely to not work so well with quartus
<ZirconiumX>
Sometimes Quartus outpaces synth_intel_alm, somehow
<whitequark>
interesting. even including startup cost?
<ZirconiumX>
Warm filesystem caches
<ZirconiumX>
Cold caches mean Quartus gets destroyed
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<ZirconiumX>
Is it okay to put `run_pass("write_verilog <...>")` within run_yosys? As in, will that work with the passed-in design or does some work have to be done before then?
<whitequark>
uhhh good question
<ZirconiumX>
Ah, run_pass takes in an RTLIL::Design
<ZirconiumX>
That'll probably work
<whitequark>
yep
<ZirconiumX>
Well, I hacked bugpoint and now I'm getting an assert from Yosys (which I've also seen from other bugpoint runs but not been able to test)
<ZirconiumX>
"ERROR: Assert `refcount_modules_ == 0' failed in kernel/rtlil.cc:605"
<mwk>
that one means you're manipulating the module list while simultanously iterating over it