clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<yosys-questions> mwk : Please have a look. I would like to add a test somewhere, but couldn't quickly figure out. Any guidance appreciated. https://github.com/YosysHQ/yosys/pull/1987
<tnt> Anyoen got a clue on https://pastebin.com/ARsviAPH "ERROR: Found error in internal cell \ice40_spram_gen.$shl$/mnt/venture-data/projects/icebreaker/ice40-playground-git/cores/ice40/rtl/ice40_spram_gen.v:0$829 ($shl) at kernel/rtlil.cc:850"
<tpb> Title: ERROR: Found error in internal cell \ice40_spram_gen.$shl$/mnt/venture-data/proj - Pastebin.com (at pastebin.com)
<tnt> This was building fine with yosys from ~3-4 days ago and doesn't with master.
<tpb> Title: ice40-playground/ice40_spram_gen.v at usb · smunaut/ice40-playground · GitHub (at github.com)
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<lambda> tnt: which yosys is this exactly?
<tpb> Title: Dynamic bit write with signed expression fails · Issue #1990 · YosysHQ/yosys · GitHub (at github.com)
<lambda> tnt: ah, missed that issue, thanks
<lambda> at a first glance it looked a lot like the stuff I've been messing around with lately (mod/div)
<daveshah> No, it isn't related to that afaics
<lambda> yeah, none of my stuff is merged yet anyway
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<ZirconiumX> Cyclone V handbook: "a DSP can do up to 27x27 multiplication"
<ZirconiumX> Quartus: "you can only have 18-bit wide arguments even in .operation_mode("M27x27")"
<ZirconiumX> :thinking:
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