<awygle>
that's very much what i was expecting to be possible, tnt. daveshah, you're saying the ODDRX2F can't be used that way?
<awygle>
or am i confused
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<tnt>
My understanding is you can't use ODDRX?F to drive the tristate pin of the io buffers. Only the data pin.
<tnt>
For ODDRX2F if you want to pack the FF controling the tristate line into the IO buffer you can use TSHX2DQA
<daveshah>
TSHX2DQA is for use with the DQ ODDR primitive only
<daveshah>
You can't use it with ODDRX2F
<daveshah>
In theory, you can't have ODDRX2F and IDDRX2F on the same pin but I don't know if that is a Diamond limitation or a hardware one
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<tnt>
huh, that's weird.
<daveshah>
Ad the OFS1P3DX and IDDRX1F, that's definitely a valid combination but iirc Diamond unpacks the FF into a fabric one
<daveshah>
* O/IDDRRX1F
<daveshah>
I don't think any tristate register is supported with the ODDRX2F
<tnt>
damn, I was planning on using that :/
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<tnt>
At least in radiant on nx, using a ODDRX2F & IDDRX2F seems to be possible (didn't test the result, but it builds).
<tnt>
I do get a warning that my tristate register where I tried using OFD1P3IX was pushed in fabric though.
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<tnt>
Diamond does indeed chokes on it :/
<tnt>
f*ck :/
<daveshah>
The only official way to get 4:1 bidir is using the DQ/DQS primitives
<daveshah>
But that needs the DQS pin to be connected correctly
<tnt>
yeah, or to even _have_ a DQS pin.
<daveshah>
Because the delay is quite configurable, connecting DQS to the edge clock signal would probably work
<tnt>
The lattic IO are just full of surprises :/
<tnt>
The DQS is only needed for the read/write pointed generation on the IDDR block right ? So I could just generate those myself ?
<daveshah>
No because they aren't connected to general routing
<tnt>
Oh so when you said connect DQS to edge clock, you meant through an external pin ?
<daveshah>
Yeah
<daveshah>
You can't get away from having the DQSBUFM crud
<tnt>
oh yeah not an option, the board I'd want to use that on already exist and don't even use the proper pins for dq groups or anything ...
<daveshah>
I can see if IDDRX2F and ODDRX2F can work together in hardware with trellis
<daveshah>
It should be a fairly small nextpnr patch
<tnt>
Basically what I want to do is run my interfaces at a multiple of the system clock, like 2x, 4x and use those serdes to do the clock crossing at the phy level. Else I'll have to do my own serdes like I do in the ice40 but that sucks :/
<tnt>
especially since if I have to pay the latency of {I,O}DDRX1F + the latency of my own serdes ...
<daveshah>
tnt: seems like the hardware does support both on the same pin (although I doubt a tristate reg would work, I haven't tried that)
<tnt>
I'm wondering why diamond doesn't allow it :/
<daveshah>
There could be some timing nasty, I only did a quick test
<daveshah>
You also can't have both an input and output delay at the same time
<daveshah>
and I think officially most common interfaces need at least a fixed delay with I/ODDRX2
<daveshah>
But it's encouraging that Radiant allows it for LIFCL. The NX IO is fairly similar to ECP5, with some wider serialisation widths added and slightly bigger delay range
<tnt>
Mmm, and if I use an IDELAY in there it will only affect the input path right ?
<daveshah>
I would imagine so
<daveshah>
The LIFCL IOLOGIC sim models have several references to "sapphire" which is the ECP5 codename
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