<Sarayan>
extract of verilog follow by extract of rtlil (generated by the current frontend)
<Sarayan>
Why is there $0\cnt[20:0] ?
<Sarayan>
and if it's just "comb the intermediate value, then update on edge", why is there the assign $0\cnt[20:0] \cnt ?
<daveshah>
I'm not sure if it helps, but there is some background on this in the Yosys manual
<whitequark>
Sarayan: yup. please read the manual, if it's still not clear, i can go into detail
<whitequark>
but it would take a long time to write in a comprehensive way, so i'd prefer if you read the manual first
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<ashfaq1717>
How to replace basic logic cells (Nand,Not etc ) with a macro cell (i.e. adder)
<ashfaq1717>
If in a design there is an adder implemented by basic logic cells i.e. nand, not, etc, how can I identify that adder and replace with a macro adder cell to replace the logic cells?
<mwk>
first of all, what exactly are you trying to do? synthesis on some weird target that has an adder macro? reverse engineering an IC?
<mwk>
right now yosys only has the extract_fa pass which gives you full adder cells
<mwk>
it would probably be reasonably easy to make another pass that takes that and tries to chain them into proper $alu / $add / whatever chains
<mwk>
but there's no such thing yet
<mwk>
my main question is how did you end up with a netlist that only has basic logic cells
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<Sarayan>
ok, found it in the manual, and I see, it's just a default. But it's good to have a default, because you don't have to prove anything w.r.t completion of paths
<Sarayan>
and yeah, that part of the manual really clarifies things, thanks for pointing me to it
<ZirconiumX>
mwk: I'm assuming from the other issues that they've filed, they're doing ASIC synthesis
<ZirconiumX>
But they're gone now, so
<mwk>
I'm assuming as much, in which the right thing to do is recognize the damn $add cells *before* they end up as gates
<mwk>
hence my questions
<ZirconiumX>
Or possibly $alu
<ZirconiumX>
But anyway
<daveshah>
The advantage of mapping them at all for ASIC is much less than for FPGA
<daveshah>
With the current state of ASIC synthesis in Yosys, the lack of optimisations caused by the hard logic is probably costing more area than they save
<daveshah>
And there isn't really a timing advantage because between full adder standard cells and a full adder out of component cells afaik
<daveshah>
Certainly nowhere near the timing advantage from an FPGA carry chain
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<ZirconiumX>
So, at present, synth_intel_alm doesn't - can't, really - support RAM init
<ZirconiumX>
That makes e.g. nMigen designs with zero-initialised RAM get turned into flops
<ZirconiumX>
But I know that if LUTRAM isn't given an init parameter it defaults to zero
<ZirconiumX>
Suppose I mark the LUTRAM as initialisable (even though it's not) and if INIT=0 instantiate a LUTRAM anyway
<ZirconiumX>
How would I fall back to flops in case INIT != 0?
<mwk>
... we need an "initializable, but only to 0" marker for rams
<mwk>
eg. xilinx ultraram is genuinely this way
<daveshah>
XCUP URAM also needs this
<daveshah>
yeah
<daveshah>
I need to check, but UltraPlus SPRAM might be too
<ZirconiumX>
Okay, it's useful to know I'm not alone here
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<tpb>
Title: memory_bram should have a "RAM initialises to zero" parameter · Issue #1958 · YosysHQ/yosys · GitHub (at github.com)
<mwk>
hmm, wasn't there an issue for that already...
<mwk>
huh, apparently not
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<daveshah>
The other outstanding issue is BRAM output register initialisation, which I tried to fix a few months ago but got too fed up with memory_bram
<mwk>
... this seems to be a general problem with fixing BRAM things
<mwk>
you know what
<mwk>
I'm getting tired of this
<mwk>
as soon as I'm done with the current FF redesign saga, I'm starting the blockram inference redesign saga
<mwk>
so help me gods
* ZirconiumX
snorts
<ZirconiumX>
Good luck, mwk
<lambda>
she's offering to lose her sanity so we can keep ours - that's bravery right there
<ZirconiumX>
lambda: you already have to lose your sanity to have a hobby such as ours
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<lambda>
ZirconiumX: fair enough - but you can always bang your head against the wall just a little harder
<ZirconiumX>
lambda: Can I use your head instead?
* attie
adds "Famous Last Words" to the playlist for this evening
<mwk>
... oh gods
<mwk>
you're going to torture me again, aren't you
<attie>
no, this one is a normal song
<attie>
also, I just discovered that MCR also did a song with that name
<mwk>
... they did
<attie>
I was thinking of the Zeromancer song
<lambda>
ZirconiumX: and here I naively thought I could escape the depths of toolchain hell by pretending to just be a user... no chance, it pulls you right in
<attie>
it's just an inoffensive rock song
<ZirconiumX>
lambda: Are you reading my Yosys synth_intel_alm thread? :P
<lambda>
what a truly pleasant development environment
<ZirconiumX>
lambda: The main reason to use Yosys for synthesis instead of Quartus is that Yosys doesn't spend forever screaming at you for slight mistake
<ZirconiumX>
s
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