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<TD-Linux> has anyone ever tried ghdl-synth + yosys as a vhdl to verilog translator?
<daveshah> Yes
<daveshah> I used it to do some simulations with iverilog
<daveshah> I've also done mixed language simulation with ghdl+yosys+cxxrtl
<TD-Linux> cool, yeah this is basically for mixed language simulation (I want to use a vhdl core with nmigen). cxxrtl would be great but iverilog would work too as I don't need speed
<daveshah> Yeah, I was using iverilog at one point because I wanted full traces and support for a vendor primitive model
<TD-Linux> do you have a repo anywhere with this in action?
<daveshah> Is the cxxrtl simulation
<daveshah> The iverilog test was a one off thing, which I think I accidentally lost when I moved to cxxrtl
<TD-Linux> oh right I saw that project on twitter!
<TD-Linux> I should try running it on my ulx3s
<Finde> how well does the ghdl+yosys+cxxrtl approach let you look back at the vhdl/verilog input?
<Finde> I'm interested in open source mixed lang sim
<daveshah> It's not perfect, things like variables are lost, but all the signals are kept through the flow
<daveshah> *VHDL variables
<daveshah> Certainly a lot better than nothing though
<TD-Linux> in my case I want to reuse an old core (tg68k) and do the rest of the design before going back and maybe redoing the core
<Finde> yeah my concern is could you realistically continue to do development on the vhdl part if you're simulating based on generated verilog
<ZirconiumX> I remember whitequark mentioning how the simulation semantics of Verilog and VHDL are different
<daveshah> ghdlsynth synthesises stuff anyway, so some degree of simulation semantics will be lost anyway
<daveshah> What you get is basically a netlist of DFFs and coarse grain cells (the "$lowercase" cells in Yosys like $add etc)
<ZirconiumX> I'm pretty sure cxxrtl has semantics that are a lot like VHDL's though
<pepijndevos> whoa, ULX3S MiSTer is a super cool idea
<pepijndevos> I did *not* see that on twitter
<daveshah> lawrie and emard ported some stuff too
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<whitequark> ZirconiumX: yep, that's correct
<whitequark> it's funny that yosys is primarily a verilog codebase but cxxrtl strongly borrows from vhdl semantics
<whitequark> vhdl simulation semantics is basically the only thing about vhdl i understand in-depth and/or like :p
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