<Zorix>
ordered the ice breaker, it looks quite nice
Bob_Dole has quit [Ping timeout: 260 seconds]
<q3k>
there's some VHDL/Verilog support plugins for IntelliJ
<q3k>
but I've never used them
forrestv has quit [Ping timeout: 256 seconds]
<Zorix>
hmm
Bob_Dole has joined ##openfpga
<Zorix>
what dev board would have something with >40 io lines?
Bob_Dole has quit [Ping timeout: 260 seconds]
<nats`>
not sure a lot of ice device have those IO available
<Zorix>
found some like LP1K
forrestv has joined ##openfpga
<Zorix>
hmm the HX8K looks good but they only have a 40 pin dev board.. that would work for one project I'm working on, but others it would not
<Zorix>
ah nm it just has one 40 pin populated header, it has 3 more, ok that does work
<nats`>
those package are really easy you'll quickly make your own board
<Zorix>
hmm, never did bga before
<Zorix>
its cool though, pretty much got everything figured out except figuring out the constraint pin naming
<Zorix>
ah, seems like it's the actual physical pin number
<TD-Linux>
the hx1k is available in an ezpz tqfp100 package
<TD-Linux>
or even tqfp144
<Zorix>
yeah, actually end goal is to create replacements for custom vintage chips in DIP and PLCC by encapsulating a tiny fpga and all the level shifting and voltage conversion
<Zorix>
I don't know if its actually achievable though with the kind of physical constraints
<TD-Linux>
with the bga packages it is
<Zorix>
was thinking it was possible yeah
<TD-Linux>
I have made DIP40 packages with level translators for all the pins in tssop
<TD-Linux>
(parts on both sides tho)
<Zorix>
oh, do you have any pictures?
<Zorix>
I actually want to cut actual legs and encapsulate everything
f003brv has quit [Remote host closed the connection]
OmniMancer1 has quit [Read error: Connection reset by peer]
OmniMancer has joined ##openfpga
lopsided98 has quit [Quit: No Ping reply in 180 seconds.]
lopsided98 has joined ##openfpga
Asu has joined ##openfpga
cr1901_modern1 has joined ##openfpga
cr1901_modern has quit [Ping timeout: 265 seconds]
Bike has joined ##openfpga
_franck_ has quit [Ping timeout: 256 seconds]
emeb has joined ##openfpga
genii has joined ##openfpga
yorick has joined ##openfpga
X-Scale` has joined ##openfpga
X-Scale has quit [Ping timeout: 260 seconds]
X-Scale` is now known as X-Scale
Guest30583 has quit [Quit: Nettalk6 - www.ntalk.de]
Guest30583 has joined ##openfpga
Guest30583 has quit [Read error: Connection reset by peer]
Guest30583 has joined ##openfpga
jfcaron_ has joined ##openfpga
Guest30583 has quit [Quit: Nettalk6 - www.ntalk.de]
Guest30583 has joined ##openfpga
peeps[zen] is now known as peepsalot
_franck_ has joined ##openfpga
OmniMancer has quit [Quit: Leaving.]
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined ##openfpga
OmniMancer has joined ##openfpga
OmniMancer has quit [Client Quit]
_franck_ has quit [Ping timeout: 260 seconds]
jfcaron_ has quit [Ping timeout: 256 seconds]
_franck_ has joined ##openfpga
jfcaron_ has joined ##openfpga
m_w has joined ##openfpga
lopsided98 has quit [Remote host closed the connection]
lopsided98 has joined ##openfpga
emeb_mac has joined ##openfpga
genii has quit [Quit: See you soon.]
miek has quit [Quit: miek]
Guest30583 has quit [Quit: Nettalk6 - www.ntalk.de]
jfcaron_ has quit [Ping timeout: 256 seconds]
<zyp>
this feels like a stupid question, but on ecp5, are there any benefits from using the dedicated pll inputs rather than the PCLK inputs, apart from leaving the PCLK input available for other use?
<daveshah>
Marginally less jitter going into the PLL, probably
<daveshah>
It would be a fairly specific application to actually care about that through
<zyp>
figured that might be the case
<zyp>
as far as I can see, the downside of the dedicated pll inputs is that they can only feed one specific PLL each
<zyp>
and the ones in the top side banks can only feed the top side PLLs, which are not present in 25F
<zyp>
I want to keep my design compatible with 25F, and I'm already out of IO in the left and right side banks :)