<zyp>
does anybody have figures on maximum power consumption for ecp5? the datasheet only specifies idle current and the lattice calculator seems to be useless without a specific design to calculate for, along with not supporting highend parts in the free version
<daveshah>
Maximum power is largely a useless concept for FPGAs
<zyp>
sure, but I still need a power budgets for sizing regulators
<zyp>
-s
<daveshah>
A device with every LUT and register running at 400MHz and almost all the routing used is going to consiume way more than a useful design
<daveshah>
The best way is to calculate what power gives 65degree rise over ambient, any more than that will be thermally constrained, if a general purpose board
<daveshah>
If you aren't pushing it hard, 1A on Vcc is more than enough
<mwk>
... you could even try to purposefully trigger metastability everywhere for extra crowbar currents!
<mwk>
okay I'll shut up now
* ZirconiumX
pets mwk
* mwk
purrs
<zyp>
daveshah, what if I am pushing it hard? :)
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<awygle>
i just copy the Versa power supply topology on all my boards lol
<zyp>
cabga381 got a thermal resistance of 19°C/W at zero airflow, meaning it could dissipate 3.4W if you allow a rise of 65 degrees
<zyp>
haven't run the numbers on the other rails yet, but 1.2W at the core rail doesn't seem like it'd come close to be thermally constrained
<daveshah>
1.2W was more of a typical unambitious design type level
<daveshah>
3W sounds about as high as it could get on a non synthetic design anyway
<zyp>
https://bin.jvnv.net/file/afyrp.png <- I'm working on a design that'll hook up a ddr3 sodimm, also planning to break out all four serdes channels
<zyp>
does that count as ambitious? :)
<daveshah>
Yeah, 3W is probably a better target for that
<daveshah>
On the thermals side, DDR3 will probably dissipate a nonneglible amount of IO power too on the ECP5 side
<zyp>
I've already made it a point to make sure the sodimm won't get in the way of a heatsink on the ecp5 if needed
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