ChanServ changed the topic of ##yamahasynths to: Channel dedicated to questions and discussion of Yamaha FM Synthesizer internals and corresponding REing. Discussion of synthesis methods similar to the Yamaha line of chips, Sound Blasters + clones, PCM chips like RF5C68, and CD theory of operation are also on-topic. Channel logs: https://freenode.irclog.whitequark.org/~h~yamahasynths
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<cr1901_modern> https://twitter.com/Foone/status/1379693949191823364 My favorite part of this is how the sound chip provides the paddle ADCs. Interesting additional feature
<Sarayan> reminds me of the POKEY
<Sarayan> "The Pot Keyboard Integrated Circuit (POKEY)[1] is a digital I/O chip designed for the Atari 8-bit family of home computers and found in Atari arcade games of the 1980s. POKEY combines functions for sampling potentiometers (such as game paddles) and scan matrices of switches (such as a computer keyboard) as well as sound generation. It produces four voices of distinctive square wave sound, either as clear tones or modified wi
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<Foone> cr1901_modern: I didn't get into it in that thread, but the NES controller is even weirder
<Foone> it's not hooked up to the sound chip... it's hooked up to the CPU
<Foone> and not like GPIO ports
<cr1901_modern> I think the sound chip is also hooked up to the CPU?
<Foone> there's dedicated silicon on the CPU to handle reading the controller ports
<cr1901_modern> The NES is like 3 chips
<cr1901_modern> RAM, PPU, and CPU?
<cr1901_modern> But yes, that level of integration was "cute" to me
<Foone> it's even weirder on the SNES, because for Reasons they were designing it to be NES compatible
<cr1901_modern> There's only one port shared between the NES and SNES memory map.
<cr1901_modern> The controller port. The protocol is backward compatible
<cr1901_modern> as well as the bit layout
<Foone> so it's still on the CPU but it has to change clock frequency to read it (or it'd go too fast for NES controllers) and also it has to read the SNES controllers in an odd order so that it reads the NES buttons first, yeah
<Foone> it's amusing because nintendo did the absolute opposite on the DS. instead of having the buttons hooked up to the CPU directly... you have to do inter-CPU communication just to read all the of the buttons
<cr1901_modern> Oh wheee lmao
<Foone> because some of the buttons are being read by the other slower CPU
<cr1901_modern> NES is ~1MHz? SNES is ~1.7-3.x MHz. Whatever backwards compatibility it had for slowing down the clock speed to read buttons in NES mode didn't survive?
<cr1901_modern> (even though yes, the SNES can and does switch clock speeds, it's not anything the NES can handle)
<Foone> good question. I don't recall off the top of my head. slightly too sleepy to remember all the details
<cr1901_modern> Okay I am wrong
<cr1901_modern> NES CPU is 1.79MHz
<cr1901_modern> Thought it was closer to 1. If the SNES accesses memory in the 2100-21ff region (B Bus), _IIRC_ it automatically gets its clock speed downgraded to 1.79MHz- compat w/ NES.
<cr1901_modern> But that's not where the controller port lives
<cr1901_modern> 400x-something?
<andlabs> yeah Foone you are probably better off using the CIAs =P
<andlabs> the pot inputs on the SID on my C128 are being reported as BAD for some reason, even with a known good SID
<andlabs> I have to go and igure out what else is wrong
<andlabs> there are two 1800pF capacitors
<andlabs> maybe one of them is dead
<andlabs> I hope it' snot he harness itself that's broken
<andlabs> also I think the POKEY on my atari 800 is broken
<andlabs> I get a constant loud buzzing which is probably coming from one ot he channels
<andlabs> of course no one makes clone SALT harnesses, unless I'm not looking in the right place?
<andlabs> yes very late followup comment
<ZrX-NoMs> Checked the analog switch between the ports and the SID?
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<andlabs> ZrX-NoMs: analog switch? which component is that?
<ZrX-NoMs> One of the two 4066s.
<andlabs> I was looking at the schematics in the service manual and it only pointed to the two capacitors being connectd to those lines (C108 and C109, ulness they're differnet numbers on my board)
<andlabs> hm
<andlabs> oh and also the C128 troubleshooting guide doesn't list my scenario
<andlabs> which is "bad controller test, good everything else, bad U5"
<andlabs> it lists "bad controller test, good everything else, bad U1" though
<andlabs> well I'll check those 4066s too somehow
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<andlabs> well I'll check those 4066s too somehow
<andlabs> also I need a C128 -> C64 PSU adapter so I can test my C64 to see if it's still reporting everything good
<andlabs> that way I can tell if it's the harness or not
<andlabs> and then verify the C128 SID is actually good on top of that
<andlabs> no one seems to be selling those right now
<andlabs> though
<Zorix> check for broken traces
<Zorix> take SID out, measure all the way from one end to the other
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<ValleyBell> dumping progress: https://vgmrips.net/misc/SN-U110-02.raw
<ValleyBell> This is a dump of the SN-U110-02 PCM card.
<ValleyBell> ".raw", because I descrambled it
<ValleyBell> I'm satisfied with this so far.
<ValleyBell> I'll probably dump all the PCM cards I have this weekend.
<ValleyBell> Interestingly, the address line scrambling is different from the CM-32P's internal PCM ROMs.
<ValleyBell> CM-32P address line order: 18, 17, 15, 14, 16, 12, 11, 7, 9, 13, 10, 8, 3, 2, 1, 6, 4, 5, 0
<ValleyBell> PCM card address line order: 18, 17, 8, 9, 16, 11, 12, 7, 14, 10, 13, 15, 3, 2, 1, 6, 4, 5, 0
<ValleyBell> The data line scrambling is the same.
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