01:06 <mastermart> https://github.com/VerticalResearchGroup/miaow/blob/master/src/sw/xilinx_sdk/main.c this is the dispatcher that deals with fetching stuff from memory, when buff does and does not ack,

01:08 <mastermart> in other words, duplets are easy to be scheduled, when two instructions are toggled from a line, and nothing else schedules, the cu2dispatch_wf on a stall does not toggle, and simulator feeds X again in this case, which corresponds to all in logic ones,

01:09 <mastermart> in such a case chip uses the last scheduled instruction of SIMD arbiter for the queues, and fetch arbiter was all ones as told.

01:15 <mastermart> so there is not a single solution but big varieety of those, can be done also like I suggested in the beginning, but scheduling the holes is not also very expensive, at least not as expensive as i feared, i mislooked the first time.

01:25 <mastermart> rember the name that this license header mentions, this guy is a purest genius in hw programming art. ziliang guo.

01:27 <mastermart> Wiscons university gace google hailing from Hong Kong himself initially, and picture also shows the fact, guy has big head and very many functional brain cells to command.

01:35 <mastermart> the variety of solutions is good, because when hw faces some type of bug or suffers under some type of malfunction, then some different solution can be used,

01:59 <mastermart> one of the most serious show stopper bug would be if it accessed instruction cache over LSU and on memory protection stall it would lock the lsu, but in miaow it is not present, cause it accesses memory bridge directly and cache controller without a texture unit/LSU.

02:19 <mastermart> but the non-blocking pci-e and axi tranasction id in the bus traffic is not a problem, the spec allows pipelined recycling of those.

02:19 <mastermart> in other words, they wrap around and do not block and many available upto 256 or more transactions buffered and wrapping around,

02:22 <mastermart> keyboard does not register stuff, Wisconsin, i head off now.

10:10 <cwabbott> anarsoul: so it turns out that the crashes were at least mostly due to something silly, apparently num_child doesn't get set automatically for ALU ops and I didn't set it manually

10:10 <cwabbott> the pass -> fail and fail -> pass is a bit more concerning there, though

10:10 <cwabbott> ideally there shouldn't be any changes from that series

10:11 <cwabbott> except for maybe tests passing because RA now succeeds

10:12 <cwabbott> I thought that when I merged the original VS control flow series that all the VS control flow piglits were passing, but maybe I missed a few?

11:55 <MoeIcenowy> anarsoul: please tag !2599 with lima

15:34 <anarsoul> MoeIcenowy: done

19:37 <plaes> .win 10

19:51 <anarsoul> plaes: wrong win

20:51 <plaes> mhm :(