<mastermart>
it does not matter on utgard based gpus cause 128pipeline stages is somewhere between 8-16 maximum instruction words
<mastermart>
and there are enough texture units 16 for them
<mastermart>
but on amd chips for instance there can be 40waves per CU, and only 16texture units, the algorithm became very complex and burned by brain edventually without knowing the queueing
<mastermart>
cause the tests in simulator is not one to one, cause miaow lacks texture unit logic
<anarsoul>
there's likely only one texturing unit on utgard
<anarsoul>
since you can fetch only one texel per clock
<mastermart>
no , this is not possible, i think opengl 2.1 requires to have at least 8 to 16
<mastermart>
but i dunno either, will look at this tomorrow
<anarsoul>
samplers
<mastermart>
but one texel per clock sort of like makes sense
<anarsoul>
not texturing units
<mastermart>
Hmm, i am not sure if i was the one who was wrong after all on #opengl
<mastermart>
i think sampler is the same as texture unit overall
<mastermart>
actually maybe not
<mastermart>
it is the ROP output probably which is fed to texture unit
<mastermart>
I am very tired today, and i drank a bit too, i have to look but if my memory is not fuzzed on this matter, i think
<mastermart>
still every bundle had it's dedicated unit for utgard for texturing too
<mastermart>
anarsoul: but yeah actually i know your fears, my docs say sm3.0 needs to have 4texunits available at least..
<anarsoul>
mastermart: utgard doesn't support sm3
<anarsoul>
it was designed for sm2
<mastermart>
which is yeah short of simd aribte
<mastermart>
anarsoul: so what happens if you try to access the texture unit1 which is the only available
<mastermart>
from another
<mastermart>
thread/warp
<mastermart>
does it stall cause the unit is allready busy?
<anarsoul>
no idea, we don't have performance counters yet, so I can't even take a look
<mastermart>
for my algorithm which i designed, this is indeed reasonably bad and limiting factor for parallelism
<mastermart>
then I should sniff, from connors referenced/citied patents probably if they mention it there, or search some arm/falanx patents from google.
<mastermart>
this clarifies quite a lot but, not everything, first sentence is that functional units 2 3 4 5 6 have access to the cache
<mastermart>
there are two pipelines also like two cores maybe?
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<mastermart>
the design does re-enter stuff, so it's all good
<mastermart>
for an example if that load misses the cache, the instruction is thrown out of the pipeline and
<mastermart>
and inserted again later
<mastermart>
anarsoul: my primary interest was stall events like deferred blocking assignments in the address calculation stalling because of no evaluation events, then the subsequent stage resets the unit
<mastermart>
and basically always fail on the register later on until the address of the backing reg is changed with WAR hazard
<mastermart>
which is of course the needed behavior
<mastermart>
they yeah kinda have different terminology or meaning for texture units, and they say they have one per pipeline, whatever it means , but barrelled lock-step functional units they have more than those 5
<mastermart>
so definitely each word has functional unit which has access to cache, and it is done in lock-step maybe?
<mastermart>
i head off to sleep, and i can not always access the channel, i am using VPN since obviously my IPs are all blocked/banned :)
<mastermart>
well it appears that utgard and midgard gpus have very flawless design, bu in fact it takes some time to get used to the weird terminolgy forks :) however as computer scientists once again this arm norway is seeming to be good group of them.
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<mastermart>
Fins make strong statements which are consistent with swedish and yankee benchmarks, and consistent as to how i see and understand and read from miaow.
<mastermart>
namely that with pipelining enabled, the full schedule of warps is asynchronous
<mastermart>
and what is more important since fetch and decode is no longer done, everything works according to other stages critical path or worst case latency to start another pipeline
<mastermart>
in other words, dispatcher is always in charge of feeding rst and clk signals asynchronously. Which is fantastic on it's own. You need not to touch the powering and frequency scaling part of the circuit at all.
<mastermart>
What i say is the cowork of api and hw designers which maybe coincidental/fluky has left the backdoor for performance in both vertex and fragment shaders, hardware designers meant all good, but maybe it was inevitable to patch up/block performance backdoors
<mastermart>
So it is only the driver in software land which is broken, old api and hw seems to provide the possibility at least in some coincidental way.
<mastermart>
It required some positiveness to be seen in life, and minor work added to identify/rediscover those ways, i was all determined and knew this is the case for some years ago allready, however i have been polishing the details ever since.
<mastermart>
and making vast set of backup plans for any hardware ever manufactured, and i start to make the code later in real hw, as job ordered from my company.
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<mastermart>
The idea is as much paranoid as one party maybe, the hdl is defined by another members of community, the hw is designed my some, the api is designed by some, if only the vendor is paranoid about selling their gradual enhancements and the api is just so gigantic
<mastermart>
they probably do not get away all clean for several reasons with blocking the way entirely
<mastermart>
Imo similarly if there is not evidence present and supporting information to bunch of persons lies, there is no results to show their superioty either, it is a matter of time when they expose their lies and fallback
<mastermart>
or fall down
<mastermart>
one commented very strikingly or genuinly (i added it to my facebook timeline) like so: They will ignore you, then they will laugh at you, then they will fight you, and then you win! My supporters have given all one sided advise to me, that this does not end simpler, once the rebeller scammer started, they will continue until stopped.
<mastermart>
cause those three symptoms sort of citied, they took of from initial stage, where bunch of people made a run up based of entire lies of course, then they ignored, then they laughed at me, then they were beaten and then i won.
<mastermart>
To the question when i quit playing due to terror, who from your superior minds to send to play and present estonian sportsmen or women i assume blank silence
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<mastermart>
and i am not interested in standing behind and representing intruguents to the world, you either show legit skills, back off or there is going to be a fight due to past criminal activity and terror towards me.
<mastermart>
better straighten up before i die due to medication long term abuse, where people responsible will be treated anyways later, and this is not funny , I chose the best med for me due to being forced to use any of them in list, but some of those meds probably allready canceled on of my good friend, put off her life candle for good.
<mastermart>
roughly 3-4 years ago if i remember that shock time properly.
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<anarsoul>
GL_INVALID_OPERATION instead of GL_INVALID_VALUE?