04:57 <rembrandt83> and I allready mentioned to derive a value from indirect cache entry that of 32bit reg, i am pretty sure according to my secondary school class which we called Permutations and Combinations subclass in maths.

04:59 <rembrandt83> you need to have 32x32 buffers so 1024 of them , since every buffer is 4bytes that means 4096 bytes, but the cache sizes on early chips were allready 4096KBs

05:03 <rembrandt83> so the only complication, since the cache bank sizes are so large is to make the logic of memory mapping on MCU/MMU and the logic to map them to shaders.

05:25 <rembrandt83> so yeah 1024 different combinations of powers of two's

05:26 <rembrandt83> in a 32bit reg or variable

05:26 <rembrandt83> 4096 of them in 64bit variable

05:29 <rembrandt83> so modern computer chip netlists are a madness of course, it is smart peoples/pupil human knowledge and persistant work to get that far

05:43 <rembrandt83> I think with weeks of work , i could propose some type of mapping scheme via couple of levels of indirections in the shader , so the scalar reg offset has indirections via dependent load or other means in vertex shader, to offset into correct VMA

05:44 <rembrandt83> most others are passed in verbatim/unmodified without indirection

05:45 <rembrandt83> but there are pretty much endless of ways, we could implement things based of my initial or preliminary braindump still though

05:50 <rembrandt83> on big projects trying something together without any coordination present like it is at the moment the case, only corporations empleyees meet and discuss things which methods to try -- seems more and more pointless and waste of time especially when terrorists like plaes are doing their fatal job.

05:55 <rembrandt83> I may post some code too, but i see people not capable to read it, and i might as well without meetings pretty much do things my own instead, cause without being able to read any code I do, you would screw up things bad

06:25 <rembrandt83> plaes is an IRC true punisher amd cloak and whatnot, terroristic to punish personalities in amoral way, expected to not punish very heavy in events that require real scoring.

17:20 <rembrandt83> https://chromium.googlesource.com/chromium/deps/mesa/+/7de552acbb188534ff74435e14e7e7e5ae3d649b/src/gallium/drivers/llvmpipe/lp_tex_sample_c.c since tmu2.v was missing texture repeat mode, i looked at Brian Paul's

17:22 <rembrandt83> llvmpile, and there the textyre repeat is nothing more then modulus operation , the remainder macro which takes parameters the coordinate and size

17:23 <rembrandt83> that can be implemented in shader fast with two subtractions

17:23 <rembrandt83> http://footils.org/2010/06/05/fast-power-two-modulo/

17:24 <rembrandt83> or using and bitwise op and one subtraction

17:25 <rembrandt83> i have covered most of the bitwise ops emulation, i can not see much of them missing yet in emulation with gl2.1 GLSL1.2 and below specs

19:01 <rembrandt83> there has been a negate modifier from vs_1.0 ps_1.0 times allready, as much as you hope me being wrong probably i am not 1+-1=0 not aka.negate applied will be 1 -0 = 1 negate applied 0 so it behaves like an XNOR gate or AND so to speak

19:10 <rembrandt83> in other words, never tested, but modulo on powers of two should be very fast on GPUs

19:11 <anarsoul> rellla: is there an easy way to trigger ppmmu fault that you're seeing?

19:18 <rembrandt83> in secondary school , logics i barely got a weak 3 to get it passed though, but as always i was under schocking terror by leftovers mostly too, as it is today the same, leftovers come to tell me that i have no rights to drink alcohol

19:18 <rembrandt83> that i have to die on drug overdose that leftovers prescribe me

19:18 <rellla> anarsoul: https://freenode.irclog.whitequark.org/lima/2019-11-24#25828265;

19:19 <rellla> and following

19:20 <anarsoul> so deqp write.use.*

19:20 <anarsoul> OK

19:20 <anarsoul> I'll try it tonight

19:21 <anarsoul> do you get the same ppmmu fault without enunes's changes?

19:21 <rellla> yes, with -n you get the 4 tests. disabling bocache should trigger the ppmmu fault.

19:21 <rellla> not sure.

19:22 <rellla> today i ignored kernel faults and tried to understand, what happens on write.use.index_array.*

19:22 <rellla> and why it fails

19:22 <anarsoul> ppmmu fault at the same address

19:22 <anarsoul> 0x79b040

19:23 <anarsoul> so it's something shared

19:23 <anarsoul> can you dump stream for the run?

19:23 <rellla> lima dump?

19:24 <anarsoul> LIMA_DEBUG=dump

19:24 <anarsoul> and then share the dump *and* error from dmesg

19:25 <rellla> sure, but i'm busy with other things atm...

19:25 <anarsoul> no worries

19:25 <anarsoul> it definitely can wait

19:26 <rellla> what i found out with the above test is, that with a vertex count of 126 a draw_arrays is triggered,

19:27 <rellla> and as soon as the nr is 127, index_size is 1 and draw_elements is done.

19:28 <anarsoul> rellla: I suspect we're freeing ctx BO to early

19:28 <anarsoul> in general that's not a good idea to share BO between different jobs if we can avoid that

19:28 <rellla> the interesting thing is, that with 127 info->max_index is 254, with 126 it's 126 :/

19:29 <anarsoul> :)

19:29 <rellla> and with 126 test is ok, with 127 it's wrong.