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<cooper__>
Wanted to let people know that my memory corruption problems *ARE* caused by a kernel misconfiguration and not the power provided to my PcDuino3 Nano.
<cooper__>
I'm currently moving from the working to the non-working config in an effort to isolate which thing I turned off that accomplished this.
<cooper__>
One question though. On the page for this board ( http://linux-sunxi.org/LinkSprite_pcDuino3_Nano ) it says that a patch was previously needed to get gigabit line speeds from this board, but u-boot now does this for you.
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<cooper__>
A small test (90MB file from SD on Nano to main machine via FTP) resulted in 12 MByte/s throughput even though a dd to /dev/null went at 20 MByte/s.
<atsampson>
Cooper__: that's me that wrote that
<cooper__>
The CONFIG_GMAC_TX_DELAY=3 parameter isn't present anywhere in my setup, so I'm wondering if it really is in u-boot.
<cooper__>
Is there some way I can verify?
<atsampson>
in your u-boot source, have a look at configs/Linksprite_pcDuino3_Nano_defconfig
<atsampson>
the CONFIG_GMAC_TX_DELAY=3 line should be in there
<cooper__>
It is.
<atsampson>
it's pretty obvious (for me, at least) if that option's not turned on, because you get massive packet loss if it's negociated at 1000Mbps -- you'll see TCP connections hanging, etc.
<cooper__>
I don't recall seeing dropped packets being reported.
<cooper__>
Just surprisingly low throughput.
<cooper__>
Connection hangs I got with the previous kernel.
<cooper__>
Which was also using old UBoot.
<cooper__>
Previous being 3.4
<cooper__>
And without that setting specified by me.
<atsampson>
linux-sunxi's 3.4, rather than Linksprite's 3.4?
<cooper__>
Indeed.
<atsampson>
then that's what I'd expect to see -- Linksprite's kernel has a patch in it to set that register, linux-sunxi's doesn't
<atsampson>
doing "nc -l -p 1111 </dev/zero" on one of my Nanos and "nc 192.168.25.148 1111 | pv >/dev/null" on another machine, I'm seeing about 30-35MiB/s reported
<cooper__>
Just did another quick test.
<atsampson>
although it does vary quite a bit...
<cooper__>
Copied the file from SD to tmpfs mount.
<cooper__>
A dd from there to /dev/null moves at 130 MB/s
<cooper__>
When I ftp from there to my machine I get 44 MB/s
<cooper__>
So network must be fine.
<atsampson>
that's not too bad, then
<cooper__>
I can definately live with that.
<cooper__>
Upping the voltage to 5.1 (it's since stabilized and is now mildly fluctuating between 5.10 and 5.12) did have some positive effect though. When I pull the power on the board the harddisks (everything's connected to the same buck converter for their 5v feed) don't suddenly spin up anymore.
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<cooper__>
Wow, you're really moving fast on those DDR tests.
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<cooper__>
Hrmm... Does the AllWinner A20 have this second level cache controller? The L2x0 PrimeCell? I found that the L210 is on ARMv5 and v6 archs but can't find if the L220 is in the v7 or any other for that matter.
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<mripard_>
Cooper__: the L2 cache is intergrated in the CPU itself
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<mripard_>
and iirc is always enabled
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<mripard_>
(at least when the caches are enabled)
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<NiteHawk>
the datasheet seems to only mention L1 cache