<ssvb>
for bi-directional lines, ODT helps to switch it between the drive and termination modes
<atsampson>
the Altera guide you linked to (which is really good, by the way; cheers for finding it!) talks about external termination for the command/address signals -- but that's with rather more chips on the bus because it's talking about DIMMs
<ssvb>
atsampson: I'm not completely sure, but believe that the address and command lines are operating at half speed
<ssvb>
I was looking for what the 2T command rate timing could possibly mean, and this PDF seems to imply that the address and the command signals are held on the bus for 2 cycles instead of 1
<ssvb>
but this pdf mentions the "quarter-rate controller" together with the 2T command rate, and not "half-rate"
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<ssvb>
oh, in fact that last Altera pdf mentions "1T/2T/4T Addr/CMD Decoder" on one of the diagram labels, so probably they mean that the "quarter-rate controller" can work with the 2T command rate in addition to supposedly the 4T command rate
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<atsampson>
it's not immediately clear to me that all the DRAM controller IP designers mean the same thing by half-rate/quarter-rate/etc...
<atsampson>
the 1T/2T command rate thing seems clear enough, though
<atsampson>
so the idea is that since your address bus is shared between (potentially) lots of chips, it can take a while to settle -- if you're using 2T timing, then you set the address, wait an extra cycle, then send the control signal, by which time all your memory chips will hopefully be seeing the same value for the address
<atsampson>
but that results in an extra cycle's latency, and halves the rate at which you can send commands (which probably doesn't matter if your commands are mostly burst read/writes anyway)
<atsampson>
the Micron docs also make it clear what the per-lane settings are really intended for -- it's when you've got a DIMM with several chips and fly-by routing, so you potentially have 20cm between the chips at the two ends
<ssvb>
yes
<atsampson>
so I guess we're probably not going to see many sunxi boards where it's actually useful, because we normally don't have those kinds of differences
<ssvb>
:)
<atsampson>
I've not done the maths to work out what the physical distances corresponding to the phase tweaks are...
<atsampson>
anyway, bedtime, I think, else my students are going to wonder why I'm not making any sense in the class tomorrow morning -- night :)
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<arie>
hi
<arie>
I'm using mpv+libvdpau-sunxi to play videos with hardware decoding
<arie>
this works, but my high bitrate videos (~28Mbps) are played too slowly
<arie>
even though I read that the maximum bitrate should be 40 or 50 Mbps
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<arie>
is there anything I can try to fix this?
<arie>
hardware is a cubietruck (A20)
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<RSpliet>
is there an allwinner DRM driver in the make? if so: could anyone inform me about the status please?
<RSpliet>
(to clarify: I'm interested mostly in display. 3D is mali, I know the status of that part)
<RSpliet>
oh, it's in the "left to be done - difficult" category on the wiki... I take it it hasn't had much love yet then
<Wizzup>
there is a simplefb
<Wizzup>
s/ a / /
<RSpliet>
Wizzup: I think I've seen that... I'll probably be confined to that one then
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<AndChat|7049>
hi, i have to use sunxi a13 uart3 with 115200 baud but with 0 error rate. with 24 mhz clock its divider is 13.02083. is it possible to get an exact divison somehow ? thanks
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<arie>
I have to leave now, but I'll read the logs and come back later
<arie>
so if anyone can help with my question from 16:44, that'd be great
<arie>
bye
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<Seppoz>
anyone know what the difference between h series and a series is
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