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<topi`_>
what's the current status of A31 support? I have a hummingbird A31 from Merrii, but last time I tried the kernel, many things were missing, and the CPUs could not be clocked higher than 1ghz (missing voltage rail support?)
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<ijc>
NiteHawk: PSCI is fundamentally an interface for nonsec to request sec to do things which it is not permitted to do (often things like starting/stopping cpus etc are limited to sec world only). The mechanism underlying PSCI (smc instruction) is, I think, only available from NS world (and traps to S world/monitor mode and monitor mode may not even be present in the CPU if trustzone isn't present). Plus when running in sec world the kernel can do all
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<NiteHawk>
ijc: thanks for the explanation. the thing that puzzled me / kept me busy for a while was that the absence of the /psci device node will prevent linux 3.19.2 from bringing up the second CPU (on sun7i / A20). so "HYP" mode is essential there
<ijc>
NiteHawk: yes, I think so. In principal someone could add native support for starting CPUs when in sec world, but NS world is just as functional, if not more (since it has hyp mode), so I guess no one would bother.
<ijc>
I suppose the sunxi 3.4 etc kernels run in sec world, which is why the option even exists in u-boot
<NiteHawk>
ijc: it looks like that - at least the mainline U-Boot page on the wike mentions specifying "bootm_boot_mode=sec" for sunxi-3.4 ;)
<ijc>
sounds about right. anyway, I'm off to brave the elements to work...
<NiteHawk>
ijc: thanks again :)
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<ssvb>
NiteHawk: hello? are you here?
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<NiteHawk>
yup. just saw you corrected the wiki :)
<NiteHawk>
ssvb: if found it very confusing - and the fact that u-boot won't offer psci without being in "nonsec" mode seemed to be documentend nowhere
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<ssvb>
NiteHawk: confusing in what way?
<ssvb>
right now you have added a slightly factually incorrect info dump to the wiki
<ssvb>
what purpose is it supposed to serve?
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<NiteHawk>
i spent nearly a day figuring out why the linux kernel wouldn't boot the second CPU on sun7i, despite being configured to support PSCI
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<NiteHawk>
as u-boot didn't provide the device tree node. sure, it was my fault (by re-/misconfiguring it)
<ssvb>
NiteHawk: u-boot defaults should work fine
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<NiteHawk>
i went for the pitfall of "secure" = "better", where it's actually more restrictive and silently drops the psci node
<ssvb>
in fact, this extra section may encourage the users to play around with their u-boot settings and breaking something
<ssvb>
imho we should not encourage bad behaviour
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<NiteHawk>
i now understand how the defaults are meant to work, but the 'silent' failures kept me puzzled for a while. i just wanted to document what i learned during my research - may not have ended up in the most suitable way...
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<NiteHawk>
i think the kernel might benefit from a warning message if ARM_PSCI is defined, but no /psci node is found
<ssvb>
NiteHawk: you are supposed to try the defaults first, and only then start experimenting
<NiteHawk>
yeah :(
* NiteHawk
= stew pit
<NiteHawk>
anyway - can you think of other/better ways to preverse that info? :)
<NiteHawk>
btw: is it technically required that secondary cores get unavailable in "sec" mode? that's part of the stuff "confusing" me
<NiteHawk>
i understand the hypervisor/virtualization issues, but a 'plain' u-boot startup launching a linux kernel shouldn't be troubled?
<ssvb>
you have already created a PSCI page, the u-boot page may say something like: "if you wonder why the 3.4 kernel needs the bootm_boot_mode variable, then check PSCI page for more details"
<NiteHawk>
that's an idea. basically, you suggest moving the "boot mode" part there?
<ssvb>
yes
<NiteHawk>
that's fine with me
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<ssvb>
the secure mode is less restrictive for the kernel, so the kernel can initialize secondary cores itself without any help from the PSCI firmware
<NiteHawk>
which 3.19.2 clearly doesn't?
<ssvb>
I may be mistaken, but I think that sun6i still does not have PSCI support
<NiteHawk>
or would i have to remove ARM_PSCI in that case?
<NiteHawk>
yes, it seems to be a sun7i (and later?) thing
<NiteHawk>
sun6i is single core, or? this 'problem' only surfaces with multiple cores
<NiteHawk>
ah, okay. i might have to recheck this stuff with a 4.x kernel - 3.19.2 (in combination with bad u-boot settings) was the main reason for my "confusion"
<ssvb>
that's what I meant about that new u-boot wiki section being factually incorrect
<ssvb>
it is even potentially harmful if the users feel encouraged to experiment on their multi-core non-sun7i devices
<NiteHawk>
i'm working on it and will describe the details on the PSCI page
<alexxy>
hi all!
<alexxy>
does wifi works on cibietruck with mainline kernels?
<ssvb>
NiteHawk: ok, thanks
<lioka>
alexxy: yes
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<alexxy>
lioka: what driver?
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<lioka>
alexxy: can't say right now, my ct at home
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<alexxy>
ok
<alexxy>
anyway it is good news for me
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<alexxy>
lioka: do you remember if it was extrenal driver or inkernel one?
<lioka>
alexxy: inkernel
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<alexxy>
is it possible to boot directly from sata on cubietruck?
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<Skylark>
not completely directly, there's no SATA code in BROM
<NiteHawk>
alexxy: not from SATA alone, you'd still need a way to load the SPL (u-boot)
<Skylark>
also i wrote a hack on top of the old 3.4 kernel that adds a /dev/rawnand, so you can use dd to update boot0 and boot1 (seriously, screw livesuit)... not sure if anyone here cares about 3.4 though
<NiteHawk>
i'd be interested to learn more about "nor" flash. from what i understand it can be attached to SPI and would be able to serve as boot code for BROM?
<Skylark>
NiteHawk: i think it can, but i have not disassembled that.. my tiny boardlet has only NAND
<NiteHawk>
the A20 datasheet at least lists that possibility. and that's exactly the lines i'm thinking along - it might be a cheapo way of adding nand boot to devices that other wise lack it (no onboard flash)
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<Skylark>
I imagine you literally put boot0 at head of NOR, but if you want I can have a closer look
<NiteHawk>
i'd have to get me some serial flash first for own experiments. i'd also expect it to be a rather straightforward load of boot0/boot1, as the SPI protocol is well defined
<Skylark>
agreed
<Skylark>
also, is it just my board, or does A20 run kind of warm
<Skylark>
my board is tiny so it dissipates less heat downwards, but still... about 800mW
<NiteHawk>
i've only got banana pi here (A20-based) in a transparent case. haven't noticed any thermal issues so far
<Skylark>
interesting - SPI NOR code has 2 variants it supports
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<cooper>
atsampson: Are you perhaps around for a question or two?
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<Skylark>
NiteHawk: ok so to answer your question
<Skylark>
BROM on A20 supports two kinds of Flash: standard SPI NOR Flash with 24-bit address (no 16- or 32-bit support), and Atmel DataFlash with 3-byte address
<Skylark>
in both of those, boot0 would live at the start of Flash at linear address 0
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<NiteHawk>
Skylark: excellent, thanks! i take it that boot0 would be responsible for loading boot1 then?
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<Skylark>
both use SPI0 on pins PC0/PC1/PC2 and chip select on PC23 i think
<Skylark>
i think so, not sure if standard boot0 comes with SPI option
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<sillysnowflake>
is there some way to transfer data over ethernet (not ip)? i don't have dhcpcd on my device...
<TheLinuxBug>
You don't have to have dhcpd to set an ip on the device
<TheLinuxBug>
manually set the ip your self to get it on the network
<TheLinuxBug>
depending on distribution you can easily set it statically
<TheLinuxBug>
for example on debian in /etc/network/interfaces
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<mripard_>
wens: I have not really looked into it yet
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<mripard_>
but yeah, it looks like there's a lot of powerdomain stuff
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<sillysnowflake>
TheLinuxBug, yeah, i've gone with such a thing but it just doesn't work..
<TheLinuxBug>
you would have to set the ip to a network you are able to use, such as a private network. If you do not have extra public ips on yoru network to use, then you will have to use an internal network to access it. Something like a small NAT network.
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<ssvb>
Skylark: thanks for updating the NAND page, this information is very interesting
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<ssvb>
Skylark: about your /dev/rawnand changes for 3.4, can we find them somewhere?
<Skylark>
ssvb: i can throw a patch your way. it's not very nice and possibly has races, although it does seem to work
<Skylark>
proves the idea at least
<ssvb>
I'm just interested in a way to write the u-boot SPL to the NAND
<Skylark>
to write boot0 you dd if=boot0.bin of=/dev/rawnand bs=8192 (if your flash has 8k pages)
<Skylark>
standard boot0 looks for boot1 at block 2 or something like that, for my flash it's dd if=boot1.bin of=/dev/rawnand bs=8192 seek=512
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<Skylark>
if you get invalid argument, see your kernel log for what it believes bs=xxx should be
<Skylark>
i really should add an ioctl for this
<ssvb>
Skylark: thanks
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<Skylark>
ssvb: a *good idea* is to test by reading an existing boot0
<Skylark>
also, during the development, i bricked my cubietruck. this is seriously possible since Hynix Flash has OTP and i think the NAND code will sometimes write to it
<Skylark>
i did not get anything useful out of first MB of /dev/nand
<ssvb>
maybe having this information would be useful in the wiki?
<ssvb>
have you checked the latest opensourced libnand code from allwinner? does it bring anything useful?
<Skylark>
no, i haven't looked at it at all - I just disassembled the bootrom from A10 and A20. if you have Hopper i can share the annotated file
<ssvb>
this is very interesting
<Skylark>
i believe the first 1MB of /dev/nand is just partition table and first partitions
<ssvb>
can you share this information via github and the links to it in the linux-sunxi wiki?
<Skylark>
at least that's what the dump looks like to me
<Skylark>
oh, the dump?
<Skylark>
let me make a flat text file from it
<ssvb>
well, maybe not the dump itself, but a nice summary would be great
<Skylark>
basically i think /dev/nand is above the block mapping table layer, and /dev/rawnand is physical blocks, and bootrom knows nothing of the table
<ssvb>
in fact, replicating this NAND read logic in the u-boot SPL would be nice and we want to be license clean
<Skylark>
i would be happy to see a completely u-boot based system
<Skylark>
i had to binary patch the boot0/boot1 to get everything working
<ssvb>
or if we can call into the BROM code to do the work for us, this would be also fine too
<Skylark>
i would worry that AW may move stuff between revisions of the CPU and not tell anyone
<Skylark>
but fundamentally it's a good idea
<ssvb>
it's not a very good idea and may be a source of some headache, but could possibly save some space in SRAM
<Skylark>
i also looked at SPI boot since N1teHawk was curious about it, so we could boot from that too
* ssvb
is only interested in being able to install u-boot in NAND, and maybe also store/retrieve DRAM timings and other settings
* ssvb
does not care about the rootfs in NAND at the moment
<Skylark>
heh, i'm stuck with 100% NAND on my board
<Skylark>
mixed feelings about that
<ssvb>
if we can probe and read boot0 from NAND and extract the DRAM parameters from it, that's already a very useful thing
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<Skylark>
oh, you can do that with rawnand i think
<Skylark>
ssvb: is it still true that A20 sucks at frequency scaling
<ssvb>
Skylark: frequency scaling CPU, DRAM or something else?
<Skylark>
mostly CPU - looking for power savings for thermal reasons
<Skylark>
my board is super tiny and the CPU gets warm
<Skylark>
doesn't seem to crash or anything but still
<ssvb>
gets warm when idle or under full load?
<Skylark>
both really, although it's a lot worse under full load
<Skylark>
more or less same system power consumption as a cubieboard2 so not that surprising, really, but it's a lot more noticeable on a small board
<NiteHawk>
ssvb: agreed. especially as PSCI is still an evolving technology / somewhat "in flux"
<NiteHawk>
btw, i've cross-checked the behaviour of sun7i (A20) and u-boot-2015.04-rc4 with linux 4.0.0-rc6. same effect when booting in secure mode - with the absence of PSCI only one core gets initialized
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<Skylark>
not sure how i'm going to test this code :(
<mauro_>
NiteHawk: Hello! I Managed to solve the problem of the File system initialization.
<mauro_>
I tried to install more RootFS on a linux kernel 3.19.2: Debian trusty 7.5 and ArchLinux too.
<ssvb>
Skylark: the easiest way is probably to use FEL boot for testing
<mauro_>
On the dmesg i could notice a lot of messages referring to the impossibility to mount the partitions of the FS due to the lack of ownership of the files
<mauro_>
something like "mount: only root can do that (effective UID is 1000) "
<ssvb>
mauro_: sounds like the rootfs tarball might have been extracted without the tar option to preserve permissions (-p)
<mauro_>
exactly
<mauro_>
that was my (silly) mistake
<mauro_>
i had my sd card not under the root ownershi
<mauro_>
and i just extracted files there. This is why all the rootFS didn't work.
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<NiteHawk>
mauro_: something else: when your 3.4 kernel was hanging during boot right after "Starting kernel..." you might have encountered an issue with newer u-boot (iirc you were using 2015.01). your u-boot may try to boot in "nonsec" mode, and you need to add a bootm_boot_mode option for 3.4 kernels - see http://linux-sunxi.org/Mainline_U-boot#Boot
<NiteHawk>
Skylark: linux 4.0 (currently -rc6) offers cpufreq support / frequency scaling for A20
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<mauro_>
NiteHawk: yes i know that mode, i solved that too. Thanks for the advices!
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