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<mickenx>
is pinebook edid (panel) connected with rsb?
<smaeul>
mickenx: no, the panel bridge is connected via r_i2c, and axp pmic is cnnected via rsb. a64 has two possible pin settings for r_i2c; PL0/1 shared with RSB, and PL8/9
<MoeIcenowy>
mickenx: edid is connected with DP AUX
<MoeIcenowy>
via the RGB2eDP bridge
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<Net147>
I noticed that if I do dual display on A20 (1080p HDMI + 4.3" LCD) with 4.19 kernel, HDMI pixel clock is correct but LCD pixel clock is incorrect. if HDMI disconnected, LCD pixel clock is correct.
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<anarsoul>
Net147: yeah, same here on A64, I suspect it has to do something with clk_rate_exclusive_get()
<Net147>
anarsoul: I suspect the the clock rates for both outputs are set before the clock rate protection is enabled
<anarsoul>
Net147: but it was broken in 4.17-4.18 as well
<anarsoul>
Net147: well, I'm not expert in DRM
<Net147>
anarsoul: was also broken in 4.16 for me
<anarsoul>
worked fine in 4.15, I haven't tried it with 4.16
<Net147>
anarsoul: at the moment I workaround by explicitly moving the clocks for HDMI and second pipeline to pll-video1 instead of sharing pll-video0 with the LCD
<Net147>
it kinda makes sense to put them on separate plls so the clocks can be adjusted more freely
<anarsoul>
Net147: IIRC on A64 HDMI PHY can be clocked only from pll-video0
<anarsoul>
:(
<Net147>
anarsoul: is that the same for LCD output?
<anarsoul>
yes
<anarsoul>
well, LCD can be clocked from PLL_MIPI, but it uses PLL_VIDEO0 as input
<Net147>
okay...
<Net147>
is there any chance 2560x1440 or 3840x2160 would work on A20 HDMI at lower refresh rates?
<anarsoul>
no idea
<Net147>
I was thinking about getting an A64 for higher resolutions on HDMI
<anarsoul>
2560x1440 works on A64
<Net147>
what refresh rate?
<anarsoul>
60Hz
<Net147>
so works straight away using EDID timings?
<anarsoul>
yes
<Net147>
which A64 board?
<smaeul>
as another data point, I've successfully done 4k 30hz on Orange Pi Win Plus
<anarsoul>
Net147: pine64-lts
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<BenG83>
R18 is supposed to be long term available from AW
<wens>
JuniorJPDJ: only AES, DES, 3DES in CBC or EBC mode, and MD5 SHA1
<JuniorJPDJ>
in all of them?
<wens>
iirc the performance is very poor
<JuniorJPDJ>
thanks wens, I'll check it
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<jaganteki>
Hi anarsoul, jernej
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<jaganteki>
Reg, SUN4I_TCON0_DCLK_REG it only work for div 6
<jaganteki>
say the parent rate is 330M and dclock 55M results 6 but if we use dclock 30M which is correct for some panels, the result div is 11 is not working
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