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<quark_>
pcbBob_: it's nowadays quite easy to solder BGA components at home. those BGA soldering stations doesn't cost that much
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<pcbBob_>
quark_: I thought about buying a ordinary toaster oven and a separate controller board which does control the on / off of the toaster so the temperature curve fits the melting point of the solder
<pcbBob_>
Besides the fact that BGA isn't really the point right now - much more the complex DDR1/2/3 interfaces I don't want to bother with
<pcbBob_>
and with BGA there usually comes 6 or more layer boards with tiny trace widths and tiny vias which I don't want to afford
<pcbBob_>
Does anyone understand this commit? https://lore.kernel.org/patchwork/patch/877044/ - did they just added the "option" for the F-Series processors but didn't actually include any source code necesarry to get linux running on those?
<aalm>
atleast f20 looks like pretty much a10, so could be it's a matter of having their dts use correct compatibles..
<aalm>
i wonder if that's f1c200s mentioned in the commit
<pcbBob_>
What does 'dts' stand for?
<aalm>
device trees
<aalm>
fdt
<aalm>
it's used to describe the hw
<pcbBob_>
they say 'Add option for Allwinner ARMv5 SoCs and a SoC suniv (which is a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600).' - so I assume the F1C100A is supported as well? I just don't know where to look at in the source code to find out how they did it
<aalm>
i suppose there's some kernel config for it?
<pcbBob_>
it gives me a memory address but it doesn't give me all of the settings and option bits (e.g. for uart or pll)?
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<pcbBob_>
Okay I make one guess: There is this 'compatible'-attribute. E.g. the ccu is compatible with "allwinner,suniv-f1c100s-ccu". So I have to search for a file called 'suniv-f1c100s-ccu'? Unfortunately there is no file with that name :(
<beeble>
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
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<pcbBob_>
I don't understand why they didn't specifiy any SPI / I²C peripherals even though the datasheet from allwinner clearly says that the F1C100S has them
<pcbBob_>
Oh I see
<pcbBob_>
That's all in the pinctrl-suniv-f1c100s
<pcbBob_>
I am getting excited :D
<pcbBob_>
it's all there
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<aalm>
pcbBob_, curious, how much have you estimated your board to cost?
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<pcbBob_>
aalm what do you mean? I think getting LQFP-128 and SDR-SDRAM TSSOP 50ish is possible on 4 layers. 4 layer PCBs from China are around 40$ for 5 pieces, so 8$ per PCB
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<pcbBob>
Any idea why there is 'suniv-f1c100s-sram-d' mentioned as being compatible in 'suniv-f1c100s.dtsi' even though 'suniv-f1c100s-sram-d' doesn't exist?
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<aalm>
pcbBob, have you cloned the sources yet? i suggest doing that, then it's simple matter of using grep :]
<pcbBob>
I downloaded it as a .zip file to my windows pc and searched for a file name 'suniv-f1c100s-sram-d'
<pcbBob>
*named
<aalm>
you might want to check linux/Documentation/devicetree/bindings/sram/sunxi-sram.txt and linux/drivers/soc/sunxi/sunxi_sram.c
<aalm>
they don't follow such naming you came up with
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<pcbBob>
I didn't came up with the naming. They came up with it and then didn't supply
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<aalm>
well, those strings are not filenames to begin with
<pcbBob>
oh okay, my bad
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<beeble>
pcbBob: getting the source via git (get the git shell from the git website) and using git grep might be an easier way for you to search the sourcetree. and you want to have an updateable tree anyway
<beeble>
depending on your layout skills and used software a ddr2/3 design isn't that hard if you stick to a single device topology. it get's a bit messier if you need a t-topology
<beeble>
doing flyby ddr3 would be even easier but them you get into bootloader ddr init code "troubles"
<beeble>
6 layer from china with defined stackup goes down to about 85 usd with enig surface and qty of 10
<pcbBob>
Why are the linux guys not just giving me the reference manual they are using for the F1C100S :(
<beeble>
but you are already using altium
<beeble>
so nothing blocking there
<pcbBob>
I thought you would say that the layout doesn't look that bad
<pcbBob>
*hoped
<beeble>
everybody starts somewhere :)
<pcbBob>
I would much rather start with a simple design and partly unknown hardware than known hardware and uber complex design with 6 layers, bgas and stuff
<smaeul>
pcbBob: what do you mean? the reference manuals are freely avalaible
<pcbBob>
I stumbled upon this one today as well and also struggled with downloading it
<aalm>
did you get it?
<pcbBob>
no, I tried to install some weird chrome plugin to download from baidu without account but it seems like they don't work anymore
<pcbBob>
after that I wanted to guy with the downloader but the download failed several times
<pcbBob>
I didn't try it since a few hours
<pcbBob>
I also don't understand why "Icenowy Zheng" didn't upload it to a public available filesharing website if he is contributing to an open source project
<aalm>
i guess i'll clone a vm for trying to dload it later today
<aalm>
maybe that is public there
<aalm>
i think i also saw it on pudn.com or something, which seems a bit similar
<pcbBob>
Maybe he should have uploaded it to the linux-sunxi wiki where all other allwinner documents are located, anyhow I don't want to rant on him if he is responsible that these chips are getting supported
<aalm>
yeah, you shouldn't :]
<pcbBob>
Oh I am sorry, I am not familiar with chinese names
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<pcbBob>
This download application want's my phone number :(
<pcbBob>
"Please enter a chinese phone number" - Okay, I am out :(
<beeble>
pcbBob: some advice if you choose to go the custom board route. before checking linux try to figure out the bootloader situation. you want to be able to build your own and have all the means to load code. getting linux running afterwards will be a lit easier if you have a good fundation
<beeble>
also if you are nit able to tune you dram setup everything can take a lot longer if you have to reverse that first
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<pcbBob_>
that's the reason why I am so keen on register addresses and stuff
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<MoeIcenowy>
pcbBob: I upload nothing
<MoeIcenowy>
for the SDKs on Baidu Pan
<MoeIcenowy>
I only provide the original link uploaded by others
<MoeIcenowy>
if you really want something, I can download for you
<pcbBob_>
Icenowy but I don't understand how you add support for a hardware with only 20 pages of documentation?
<pcbBob_>
I also wrote you an email today :D
<MoeIcenowy>
pcbBob: F1C100s has the same die with F1C600, but not the same with F1C100
<MoeIcenowy>
pcbBob_: by looking at any source available
<MoeIcenowy>
and the F1C600 is in fact a F1C100s with different string on it
<pcbBob_>
So that does mean that I can basically copy the register addresses from the F1C600 300+ pages manual if I want to work with a F1C100s?
<MoeIcenowy>
yes
<pcbBob_>
The F1C100S also has DDR-RAM built in if I am not mistaken so no need for SDR-RAM memory controller specification
<MoeIcenowy>
The controller handles both SDRAM and DDR1
<pcbBob_>
originally I planned on using the F1C100A because I wanted to learn routing SDRAM interface
<pcbBob_>
oh okay
<pcbBob_>
Would you say it is possible to work with the F1C100A from the F1C600 manual?
<MoeIcenowy>
yes
<MoeIcenowy>
they're also the same die
<MoeIcenowy>
but for SDRAM you will need to look at Allwinner source/binary
<MoeIcenowy>
there's no manual for SDRAM controller
<pcbBob_>
at which source code are your referring too?
<MoeIcenowy>
please find it by yourself
<MoeIcenowy>
collect as many Allwinner SDKs as possible
<pcbBob_>
thanks alot, if you say it's possible to mostly work with the F1C600 manual apart from the SDRAM controller I will try it out
<MoeIcenowy>
Allwinner usually use the same die in many of their products
<pcbBob_>
I already thought about it but then maybe the re-arranged the address space or something
<MoeIcenowy>
I don't think it easy to re-arrange address space without retape the dire
<MoeIcenowy>
s/dire/die
<MoeIcenowy>
Usually Allwinner only differ renamed chips by a "bonding id"
<pcbBob_>
I guess it makes sense not to re-design every chip you sell
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<pcbBob_>
So I assume flashing the internal ROM of the F1C100 is done via JTAG? Even though I don't find any PIN labeled "TDI" or "TDO" in the manuals
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<MoeIcenowy>
pcbBob_: internal ROM?
<MoeIcenowy>
I think it's not flashable
<pcbBob_>
The F1C600 tells me it has 32K "BROM"
<MoeIcenowy>
this is mask ROM
<MoeIcenowy>
not flashable
<MoeIcenowy>
it's fixed when the chip is taped out
<pcbBob_>
oh
<MoeIcenowy>
BTW I'm sure F1C100s has JTAG
<MoeIcenowy>
it's muxed with SDC0
<MoeIcenowy>
I used JTAG to debug when bringing up U-Boot for F1C100s
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<pcbBob_>
Oh, so you are telling me DBG_CK is JTAG-CLK and DBG_DO is TDO?
<MoeIcenowy>
should be
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<pcbBob_>
I thought I would connect my J-Link JTAG programmer to the F1C100A and program my .hex file to the ROM :( Suddenly it starts to get way more complex in my mind with getting my code to a flash memory and stuff
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<pcbBob_>
Is it possible to program it "bare-metal" even without u-boot and basically write all hardware initialization code yourself without too much effort?
<pcbBob_>
with "too much" I mean if it would take several months to figure everything out
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<KotCzarny>
yes
<KotCzarny>
but depends on what you need
<KotCzarny>
but then you will be duplicating what uboot does
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<pcbBob_>
I thought uboot would basically prepare the CPU and RAM to run the linux kernel. If I don't want to run it, do I need to do everything what uboot does?
<KotCzarny>
then you are probably need microcontroller, and not a soc
<KotCzarny>
uboot can prepare hardware and run ANY arm binary
<KotCzarny>
it doesnt have to be linux
<pcbBob_>
there is no microcontroller having as much processing power as the ARM9 or Cortex-A CPUs
<KotCzarny>
not true
<KotCzarny>
there were few new
<pcbBob_>
linux is also just "code" being executed, why shouldn't it be my code?
<pcbBob_>
KotCzarny okay, maybe there are. But not for 2$
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<smaeul>
pcbBob_: the short answer is that if you want to use high speed peripherals (storage, video, etc), then you want to use u-boot to load your application
<smaeul>
and if you don't want to use those peripherals (you just need CPU and GPIO/SPI/I2C/etc.), then you want to use only the SPL part of u-boot to initialize the DRAM for you and load your application
<pcbBob_>
okay, that sounds reasonable
<pcbBob_>
So there is this "LicheePi Nano" board which is using uboot from here (https://github.com/Lichee-Pi/u-boot). So I guess I have to figure out how to get just the SPL part from it?
<pcbBob_>
the LicheePi Nano uses the F1C100S
<aalm>
i'd suggest starting w/the whole thing, once your code has what it needs, you can leave just the spl and replace u-boot with your app
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<aalm>
pcbBob_, ^it would also mean less reflashing the thing when u-boot likely provides more than one way to load the next stage, which is nice with initial bring up where bugs/errors _will_ happen.
<pcbBob_>
by the way: flashing. How does it work? I once tried "bare metal" with the Raspi B+, and "flashing" basically was putting the SD-card into my PC, copying the binaries, sticking the SD card back into the pi and than see what happens. I assume this would be the same way here?
<aalm>
i think most armv5 socs i've had have booted off of spi flash
<pcbBob_>
The F1C100S has JTAG hardware, at least it is listed in the documentation, and it seems there are some pins muxed with JTAG
<aalm>
while the brom might support sdcard too
<pcbBob_>
so I would program the SPI flash via UART from the PC?
<aalm>
likely, or usb, but those are soldered on pcb..
<aalm>
usually
<aalm>
i guess the sdk will reveal your options w/boot sources
<aalm>
idk. if it's a function of brom, or u-boot, but atleast later socs do support booting over usb(otg)
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<smaeul>
from the manual:
<smaeul>
Support system boot from SPI Nor/Nand Flash, and SD/TF card
<smaeul>
● Support system code download through USB OTG
<smaeul>
pcbBob_: there's a usb monitor in the BROM (called FEL) that you can use to download code into SRAM and run. that code could be u-boot, your application, or an SPI flasher program
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<[TheBug]>
MoeIcenowy: if you ever want me to host ANY code /links etc related to LicheePi * let me know I can make you an sftp or something on that server for you to use
<[TheBug]>
fALSO: g'day
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<pcbBob_>
This is so complex I can't wrap my mind around it, yet. It is amazing how such complex hardware can be handles by u guys. Much respect
<pcbBob_>
Like I would connec the F1C100S via usb to my PC. The F1C100S would be a "slave" and show up with a file system and write receiving files to the SPI flash? Is that how it would work?
<aalm>
pcbBob_, there's a tool for the FEL thing, i think you want to be running linux (in a vm is ok i think) for that, and i guess the brom would be too small to contain fake fs drivers etc. needed for that
<smaeul>
pcbBob_: it would show up as a usb "slave", yes, but there's no filesystem abstraction. you're just running baremetal
<smaeul>
but after it's in SRAM, that's the end of what the BROM helps with
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<smaeul>
so for the "SPI flasher program" suggestion, what you could do is load u-boot via FEL, run it, then connect to a UART console and use the `sf` command included in u-boot
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<pcbBob_>
I am going back and forth in my mind: Should I dump the SDRAM configuration and go with the F1C100s (which already has a running uboot due to the LicheePi Nano) or should I go with the F1C100A which is 1/3rd the price on aliexpress but I don't know of any uboot initializing the controller with SDR-SDRAM
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