sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<_florent_> sb0: I still haven't received the sayma boards but tracking has been updated, I expect to have them today or tomorrow...
<GitHub145> [artiq] jordens commented on issue #764: ping https://github.com/m-labs/artiq/issues/764#issuecomment-312576221
<GitHub146> [artiq] jordens commented on issue #769: ping https://github.com/m-labs/artiq/issues/769#issuecomment-312576270
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<key2> sb0: yosys helps me to translate verilog into a json tree
<key2> sb0: I actually gave it a try, converted verilog generated from migen into json after synth with yosys, and simulate it by simulating the primitives. works quite well
<sb0> key2, if you use migen you already have a tree, and a simpler one than verilog's
<key2> sb0: not if I have imported verilog files
<key2> such as a lm32 for example
<key2> also yosys supports importing netlist directly
<cr1901_modern> key2: There is an EDIF backend for migen; you could compile lm32 in yosys to EDIF, and then do the same for your migen design. But you'd have to resurrect the "mist" backend which hasn't worked for ages
<cr1901_modern> Actually, wait. No that won't work, nevermind
<cr1901_modern> EDIF is device-specific
<key2> what am interested in is to speed up by using GPU
<cr1901_modern> Well, for the time being I'd agree its best to convert migen to verilog and then sim that.
<cr1901_modern> key2: Did you sim yosys primitives on a GPU?
<key2> those are easy
<key2> and/or/not/xor...
<cr1901_modern> Still I have trouble visualizing how to speed up calculations on a GPU which are heavy on dependencies; if you change one signal in your design, many other signals need to change in response at that immediate point in simulation time
<cr1901_modern> And as always if you have combinatorial loops you're screwed
<cr1901_modern> combinational* bleh (just woke up. Perhaps I should chat later)
<sb0> and how are combinatorial loops a lesser problem on FPGAs?
<cr1901_modern> sb0: I think they're two names for the same thing (I just reflexively correct myself when I say combinatorial)?
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<sb0> I think so
<sb0> how does TNT take over a week to deliver from PL to FR?
<key2> sb0: you're in FR or HK currently ?
<sb0> HK
<key2> k
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<GitHub179> [artiq] jbqubit commented on issue #770: With recent updates repository/demo_2tone.py loads in < 2 seconds. OK.... https://github.com/m-labs/artiq/issues/770#issuecomment-312746720
<GitHub199> [artiq] jbqubit commented on issue #765: This bug persists in 3.0.dev+1207.g5b26e5de. Second call to config channel is silently dropped without delay.... https://github.com/m-labs/artiq/issues/765#issuecomment-312748287
<GitHub16> [artiq] jbqubit commented on issue #769: I no longer get this error with build 3.0.dev+1207.g5b26e5de. ... https://github.com/m-labs/artiq/issues/769#issuecomment-312750243
<GitHub151> [artiq] jbqubit closed issue #769: ad9154 bad CODEGRPSYNCFLG https://github.com/m-labs/artiq/issues/769