sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub181>
[artiq] sbourdeauducq commented on issue #780: We'd rather not merge it because we don't want to maintain KC705+EEM support and especially not mix it with the phaser target, but it looks fine for your local tests. https://github.com/m-labs/artiq/issues/780#issuecomment-314947900
<Ishan_Bansal>
attie: Entrophycoder() is the submodule and RLEDatapath() is the main module.
<attie>
ok
<attie>
have you tried without the CEinserter annotation on the submodule?
<attie>
it doesn't have any statements yet so it may get confused
<Ishan_Bansal>
yup that works.
<Ishan_Bansal>
but I want both to be synchronized on the same clock. Does it happen even without adding common clocks to both the modules ?
<attie>
by default, everything is on the same clock
<attie>
the default clock is inferred
<attie>
if you want different clock regions, you have to create them manually
<Ishan_Bansal>
Than what is the need of the @CEInserter ?
<attie>
if you want to be able to stall a submodule from outside
<attie>
for instance, in my design I have a pipeline that involves several floating point operations
<attie>
@CEInserter will add a clock enable signal to all sync statements
<attie>
in effect, it will add a new signal to the module: self.ce = Signal()
<attie>
and then it will change all statements in self.sync to "If(ce, <original statement>)"
<attie>
so e.g. if your submodule is just a simple (integer) adder, it has inputs op_a and op_b and output res
<attie>
and the statement self.sync += res.eq(op_a + op_b)
<Ishan_Bansal>
Also why cant we have list comprehensions in migen ?
<attie>
what do you mean?
<Ishan_Bansal>
like why we are restricted to write for loop in a single line in migen, unlike other programming languages ?
<attie>
migen isn't a programming language
<attie>
migen is a collection of python classes
<attie>
you are restricted by what python allows you to do to objects
<attie>
how much background do you have in python? and in verilog?
<Ishan_Bansal>
What I want to say is that we are able to write so in python, however while writing inside the self.sync block writing the same block will give you an error saying all values are not migen.
<attie>
yes, because you are adding elements of class migen statement to a list.
<Ishan_Bansal>
I am moving to my third year, I learned verilog during one of my courses in my 3rd sem.
<attie>
I think it will be easier if you understand how migen generates the verilog code
<Ishan_Bansal>
and about python I often used this during my two years.
<attie>
when you are writing migen, you are only ever making lists of objects.
<attie>
you are writing self.sync +=
<attie>
this is appending to a list.
<attie>
the operator verifies that the objects you are appending are of the correct class: a migen statement.
<attie>
if you try to append something that is not an object of the correct class, you will see that error.
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<attie>
at the end, the last thing you do in your toplevel is verilog.export(topmodule).
<attie>
when you call this function, it will go through the lists comb and sync
<attie>
for each element, it will generate a corresponding verilog code.
<attie>
so if you say self.comb += a.eq(b+c) it will output "always @(*) begin a = b+c end"
<attie>
if you say self.sync += a.eq(b+c) it will output instead "always @(posedge sys_clk) begin a = b+c end" (not quite correct syntax but you know what I mean)
<attie>
actually it will also add a reset
<attie>
so "always @(posedge sys_clk) begin if sys_rst then a = 1'd0 else a = b+c fi end"
<attie>
something like that
<attie>
the migen statements and the verilog statements are almost 1 to 1
<attie>
migen is just much shorter to write, and you can use python to do more powerful parametrisation than verilog allows
<attie>
but fundamentally, you just create objects that translate to these two types of lines in verilog
<attie>
and you collect them in a list that the export function will iterate over
<Ishan_Bansal>
Is Ok.
<attie>
so simply apply the rules you know from python about what you are allowed to do to objects and it should be quite clear what happens.
<attie>
for instance, see the difference between the following two statements:
<attie>
self.sync += If(a, b.eq(c)).Else(b.eq(d))
<attie>
self.sync += b.eq(c) if a else b.eq(d)
<attie>
both are correct.
<attie>
can you tell me what verilog will be generated for each?
<attie>
also what can you infer about a in each case?
<Ishan_Bansal>
attie: in the first case it will generate always@(posedge sys_clk) begin if (a) b=c else b=d end
<Ishan_Bansal>
In the second case same code is been generated
<Ishan_Bansal>
I think
<Ishan_Bansal>
Because both at the core level mean the same