sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub135> [artiq] jbqubit commented on commit 94ee488: Thanks for the update. https://github.com/m-labs/artiq/commit/94ee48860a8f22981e2430e062e60c140b421f3b#commitcomment-23127003
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<cr1901_modern> sb0: Have you sincerely met anyone who likes labview?
<sb0> yes
<rqou> labview is fine if you only use it for what it was intended for
<rqou> but the problem is that no real programs are entirely dataflow
* rqou interned at NI
<rqou> there was a decent amount of labview abuse there :P
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<sb0> rjo, what is opticlock going to use to generate the trapping field?
<rjo> sb0: cylindrical trap and then later maybe a linear trap
<sb0> rjo, and what drive electronics?
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<sb0> rjo, is the scope less crashy now? mntng has updated it
<rjo> sb0: urukul for rf and some ptb hv for dc
<sb0> ah, neat
<sb0> I suppose Urukul needs some sort of amp?
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<rjo> power amp and autotransformer.
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<sb0> who's making those?
<sb0> PTB?
<rjo> yes.
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<GitHub83> [artiq] XiaobudianChen opened pull request #786: Merge pull request #1 from m-labs/master (master...master) https://github.com/m-labs/artiq/pull/786
<GitHub49> [artiq] XiaobudianChen closed pull request #786: Merge pull request #1 from m-labs/master (master...master) https://github.com/m-labs/artiq/pull/786
<GitHub139> [artiq] XiaobudianChen opened pull request #787: Merge pull request #1 from m-labs/master (master...master) https://github.com/m-labs/artiq/pull/787
<GitHub153> [artiq] XiaobudianChen closed pull request #787: Merge pull request #1 from m-labs/master (master...master) https://github.com/m-labs/artiq/pull/787
<GitHub193> [artiq] jordens commented on issue #787: @XiaobudianChen You are hitting a high multiplication factor on ARTIQ. If you want to practice with git/github, please feel create yourself a few sandbox repositories instead. https://github.com/m-labs/artiq/pull/787#issuecomment-315730599
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<sb0> rjo, if the scope no longer crashes, i'd like to use the solid state relay on a chinese programmable power supply that has the same problem
<GitHub173> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/vQbiy
<GitHub173> misoc/master d6f86c0 Sebastien Bourdeauducq: integration: fix CSR group Rust declarations
<bb-m-labs> build #228 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/228
<rjo> sb0: hangs in different way. but i don't need the scope right now. go ahead and have the switch.
<larsc> do you know if names for generate for-blocks are required by the verilog standard, or are they optional?
<rjo> larsc: no idea. where do the experts for exotic verilog questions hang out? here?
<larsc> maybe
<larsc> I'm just asking because altera tools require them
<larsc> haven't seen any other tool that does
<sb0> larsc, do you have the standard document?
<larsc> sb0: thanks
<larsc> looks like it is mandaroy
<larsc> mandatory
<larsc> but only for for-blocks
<larsc> for if-blocks its optional
<larsc> sb0: btw. you'll like this in altera you can completely bypass the hardware PCS
<larsc> if you want to
<sb0> larsc, more than with xilinx?
<larsc> no sure if it is more, you just get clock and data which directly come from the serdes as far as I understand
<larsc> downside, quartus eats even more memory than altera
<GitHub183> [artiq] jbqubit commented on issue #785: The meta.yaml version should match that used by the M-Labs bb. Besides nagging users to update conda, in the event that the conda team introduces a bug with a conda upgrade the meta.yaml can prevent users from upgrading to a buggy version. ... https://github.com/m-labs/artiq/issues/785#issuecomment-315790705
<whitequark> huh, I think I found a bug in Python
<GitHub134> [artiq] jbqubit commented on issue #784: I reported the Issue because I had seen the message 'Couldn't find index page for 'asyncserial' (maybe misspelled?)' for several weeks. I upgraded conda to 4.3.22 and now the error message is gone. So you're right, it was a conda bug. https://github.com/m-labs/artiq/issues/784#issuecomment-315792709
<sb0> of course, with vivado 2017.2, the xilinx transceiver garbage randomly corrupts some data. i expected nothing less.
<whitequark> sb0: are you using the board?
<sb0> yes
<whitequark> ETA until free?
<sb0> 15min
<whitequark> ok
<GitHub170> [artiq] jbqubit commented on issue #780: > See I/O entries elsewhere that also use differential signaling.... https://github.com/m-labs/artiq/issues/780#issuecomment-315795114
<sb0> almost done
<sb0> whitequark, done
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<GitHub129> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/9045b4cc19da26f95e5d8c7db44a8c7c7e35279b
<GitHub129> artiq/master 9045b4c Sebastien Bourdeauducq: drtio: initial firmware support for multi-link
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<GitHub75> [artiq] sbourdeauducq commented on issue #780: Are you writing to the correct RTIO channel number? https://github.com/m-labs/artiq/issues/780#issuecomment-315813147
<GitHub96> [artiq] sbourdeauducq commented on issue #785: Have you tested it? When the user has already installed another version of conda, and then installs ARTIQ, does conda upgrade/downgrade itself *and then* installs ARTIQ? If not, then it won't work as you propose. https://github.com/m-labs/artiq/issues/785#issuecomment-315813886
<GitHub43> [artiq] sbourdeauducq commented on issue #785: Have you tested it? When the user has already installed another version of conda, and then installs ARTIQ, does conda upgrade/downgrade itself *before* installing ARTIQ and its dependencies? If not, then it won't work as you propose. https://github.com/m-labs/artiq/issues/785#issuecomment-315813886
<bb-m-labs> build #723 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/723
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<sb0> _florent_, what is the status of the multi-channel transceiver code? did you push the latest version?
<bb-m-labs> build #527 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/527
<bb-m-labs> build #1624 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1624
<GitHub176> [artiq] jbqubit commented on issue #780: > PHYs "lpc_vhdci_ext0" 0 to 7 don't register properly as RTIO channels. That is "sma_ttl_diff" and "user_led" are RTIO 0 and 1.... https://github.com/m-labs/artiq/issues/780#issuecomment-315824184
<GitHub58> pdq/master 8b6cb51 Robert Jordens: examples: clean up, add device_db.pyon...
<GitHub58> pdq/master 96f8a52 Robert Jordens: doc: links/refs to migen/misoc/artiq code and examples...
<GitHub58> pdq/master 87c121d Robert Jordens: doc: fix version number
<GitHub58> [pdq] jordens pushed 3 new commits to master: https://github.com/m-labs/pdq/compare/335fc08408ae...8b6cb51d3a63
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<GitHub89> [pdq] jordens pushed 2 new commits to master: https://github.com/m-labs/pdq/compare/8b6cb51d3a63...02e01c2f4b14
<GitHub89> pdq/master 02e01c2 Robert Jordens: testbench: use nose to run them
<GitHub89> pdq/master 2df4b77 Robert Jordens: {write,read}_{config,frame,...} -> {get,set}_......
<GitHub197> [artiq] jbqubit commented on issue #785: >Adding the conda version constraint will save everybody time as it will flag an outdated version of conda. ... https://github.com/m-labs/artiq/issues/785#issuecomment-315857840
<GitHub144> [pdq] jordens pushed 1 new commit to master: https://github.com/m-labs/pdq/commit/2992af09d0dc8873a4dbd63d4c0ebdc90f2cff56
<GitHub144> pdq/master 2992af0 Robert Jordens: cli: don't interpolate without scipy
<GitHub156> [artiq] hartytp opened issue #788: Urukul-Novogorny Servo https://github.com/m-labs/artiq/issues/788
<GitHub191> [artiq] hartytp opened issue #789: Kasli Support https://github.com/m-labs/artiq/issues/789
<GitHub114> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/d96c2abe442ef3db58bb8000acca21277d147379
<GitHub114> artiq/master d96c2ab Robert Jordens: pdq: read/write_reg -> get/set_reg...
<GitHub124> [artiq] jbqubit commented on issue #780: I pushed to a jbqubit fork of ARTIQ. It makes for easier-to-read source. This is what I'm using. Also, I don't see differential pulsing of sma_ttl_diff. ... https://github.com/m-labs/artiq/issues/780#issuecomment-315866837
<bb-m-labs> build #724 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/724
<bb-m-labs> build #528 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/528
<bb-m-labs> build #1625 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1625
<GitHub121> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/4c809f956c9f7eb9b5eec901065a6c1734acc5eb
<GitHub121> sinara/master 4c809f9 Greg: boards photos
<GitHub117> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/e429950ffb2276d33d2698d2c597c14e46baac61
<GitHub117> sinara/master e429950 Greg: added SMA DIO photo
<GitHub23> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/acd216cc9ab7127976e5bb5ae731ddac228a1fcf
<GitHub23> sinara/master acd216c Greg: rj45
<GitHub29> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/d7ed52be1098f4a3264285fac0d7878c8d860a39
<GitHub29> sinara/master d7ed52b Greg: vhdci carrier
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