sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<ashafir>
[smoltcp] i see there is timestamp added to the Device receive/transmit fn. TIVA h/w has IEEE 1588 timestamp logic in h/w. is it worth adding of this to the driver?
<ashafir>
also iface.poll(&mut socket_set, clock.elapsed()) shall it be the same time format (from the same h/w system time module)?
<GitHub105>
[artiq] jbqubit commented on issue #807: I understand that that users-who-care should implement graceful termination. All the same this schizophrenic behavior shouldn't be possible. Full-scale noise may be hazardous in some applications especially given how common it is in physics labs to use wide-band amplifiers to drive sensitive loads. For example, it's not uncommon to operate resonant devices with high gain away near to resonance including pi
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<GitHub154>
[artiq] jordens commented on issue #807: Graceful termination is not a safety feature for your hardware constraints. That would be completely mismatched. The number and severity of hardware constraints is irrelevant. Forbidden parameter ranges are arbitrarily complex. You have to take care of them yourself, in software, in gateware, or in hardware.... https://github.com/m-labs/artiq/issues/807#issuecomment-319089910
<key2>
rjo: thx
<key2>
can I tell self.specials.mem = Memory() to not use BRAM but distributed ram ?
<rjo>
key2: no currently. but passing through attributes (we have them on Signal()) to the memory element sounds like a good idea.
<rjo>
then you could do it.
<key2>
rjo: and what happen if I do something like [Signal(8) for _ in range(100)] or Signal(8*100) and read/write using a Case statement
<key2>
would it be what the tools ends up doing when doing distributed ram or it's not optimized
<rjo>
dunno. try it. but i'd assume that it won't be able to recognize this as a BRAM and potentially not even as a resonably fast distributed RAM pattern.
<rjo>
key2: but i remember these things to be recognized as RAM/ROMs in vivado.
<key2>
fact is that I don't want it to be recognized as BRAM
<key2>
as i need my bram
<key2>
i want it to use LUTs
<key2>
basically, in verilog, if I do something lile "reg [7:0] myram [99:0]" is it the same as having 100 "reg [7:0]" ?
<GitHub82>
[artiq] jordens commented on issue #807: For the phase and frequency interpolators overflows are natural and intuitive. For the amplitude/offset, they would be expensive to detect and report. https://github.com/m-labs/artiq/issues/807#issuecomment-319110530