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[artiq] whitequark commented on issue #776: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 12. For example, the following two ports in this bank have conflicting VCCOs: ... https://github.com/m-labs/artiq/pull/776#issuecomment-314468476
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[artiq] sbourdeauducq commented on issue #778: We don't lose precise exceptions with SRTIO. Underflow errors are exactly the same as before. Sequence errors are usually not an error anymore, decreasing timestamp in a channel is only an error when we run out of usable FIFOs to "rewind" the timeline (and that one error can be precise). Collision errors must be asynchronous, but they already are in ARTIQ-3 to accommodate DRTIO requirements. http
<GitHub44>
[artiq] sbourdeauducq commented on issue #778: We don't lose precise exceptions with SRTIO. Underflow errors are exactly the same as before. Sequence errors are usually not an error anymore, a decreasing timestamp in a channel is only an error when we run out of usable FIFOs to "rewind" the timeline (and that one error can be precise). Collision errors must be asynchronous, but they already are in ARTIQ-3 to accommodate DRTIO requirements. http
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[artiq] hartytp commented on issue #778: AFAICT, Proposal 1 ("Only allocate space on the master for the DRTIO channels that are actually used") seems to be a better fit to our use cases than SRTIO because:... https://github.com/m-labs/artiq/issues/778#issuecomment-314510282
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[artiq] hartytp commented on issue #778: AFAICT, Proposal 1 ("Only allocate space on the master for the DRTIO channels that are actually used") seems to be a better fit to our use cases than SRTIO because:... https://github.com/m-labs/artiq/issues/778#issuecomment-314510282
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[artiq] dhslichter commented on issue #778: I need some time to think hard about this, and I would also recommend including others like @dleibrandt @amhankin @r-srinivas @dtcallcock in the thought process. ... https://github.com/m-labs/artiq/issues/778#issuecomment-314552190