05:54 <sb0> whitequark: what is your local patch for running pythonparser with 3.7?

09:33 <hartytp> sb0: you mean because the NRT SPI bus is controlled by CSRs, which can be written to/read from over DRTIO?

09:34 <hartytp> can you remind me what the status of documentation for that is? Or, where can I find an example of that?

10:05 <sb0> hartytp: look for NRTSPIMaster

14:09 <whitequark> sb0: https://paste.debian.net/1064566/

14:32 <sb0> _florent_: shouldn't jsync meet setup/hold at the FPGA?

14:34 <sb0> whitequark: ok

14:36 <sb0> _florent_: right now it's just getting the bare signal from the I/O and using it to control several FSMs, without any sort of synchronization. or am I missing out something?

14:38 <sb0> _florent_: or, if it doesn't have to meet setup/hold, it should be synchronized with MultiReg before being fed to the different FSMs

14:39 <sb0> right now, the FSMs aren't even guaranteed to start at the same time. worse, depending on the synthesizer output and timing of jsync, you can even corrupt FSM state entirely.

14:39 <sb0> whitequark: will nmigen forbid this kind of thing?

14:39 <sb0> including with i/o

15:07 <whitequark> sb0: that's the idea, yes

15:07 <whitequark> all external inputs are asynchronous

15:55 <sb0> _florent_: "Each receiver must locate K (K28.5) characters in its input data stream. After four consecutive K characters are detected on all link lanes, the receiver block deasserts the SYNCOUTx± signal to the transmitter block at the LMFC edge.The transmitter captures the change in the SYNCOUTx± signal, and at a future transmitter LMFC rising edge, starts the initial ILAS."

15:56 <sb0> this seems to say that ILAS should start when SYNC is *low*?

15:57 <hartytp> sbo: thanks, that's just what I wanted

16:11 <hartytp> sb0: okay, I see roughly how that works