03:59 <bb-m-labs> build #2459 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2459

04:03 <bb-m-labs> build #2935 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2935

10:53 <keesj> acathla: the uart-> wishbone interface is indeed pretty nice to debug and do stuff

11:56 <_florent_> Hi, i just created a #litex freenode channel for LiteX & Cores related discussions, feel free to join for questions/issues related to this.

12:39 <keesj> cool

13:01 <hartytp_> sb0 ping

13:05 <hartytp_> you made some comments in an email a while back: "Another thing about DRTIO in general: the skew from the transceiver clock input pins to TXOUTCLK (used as RTIO clock), on both KU and A7:"

13:05 <hartytp_> ...

13:06 <hartytp_> am I right in thinking that we could drive the DRTIO clock directly from the MGTREF using a BUFG_GT on the IBUFDS_GTE ODIV2 port

13:07 <hartytp_> wouldn't that give deterministic phase?

13:08 <hartytp_> If I follow your point correctly, we currently clock the local rtio logic from the transceiver TXOUTCLK, which is derived from the CPLL output via an unsynchronised divider

13:08 <hartytp_> what's the advantage of doing that?

13:19 <hartytp_> also https://github.com/sinara-hw/Sayma_RTM/issues/16#issuecomment-459927773

13:19 <hartytp_> " * DDMTD on Ultrascale with one clock from the GTH and one clock from an I/O bank exhibits high peak-to-peak jitter and unexplained intermittent skews that are not corrected by averaging"

13:21 <hartytp_> that's a bit scary. Is the configuration you mean here, having one DDMTD input from an LVDS input and the other input being the transceiver clock internally routed to the DDMTD DFF? Does this depend on which IO is used and where the DDMTD DFFs are located on the FPGA?

13:22 <hartytp_> is it better to use externally route the recovered clock to an IO pin and use two IOs on the same bank for the DDMTD? (or, don't know?)

13:22 <hartytp_> also:

13:23 <hartytp_> 1. what are you discussing with Xilinx, and did they have anything useful to say

13:24 <hartytp_> 2. you mention GC pins and BUFGs. Where do they come into this?

13:24 <hartytp_> 3. if you did add a timing FPGA onto Metlino, how would that work then Sayma is connected to the master over SPF?

13:25 <hartytp_> basically, I'm trying to make sure I understand your observations and any implications they have for WR plans...

16:21 <_whitenotifier-9> [nmigen] sam-falvo commented on pull request #22: Updated user guide introduction for nmigen. - https://git.io/fhFBQ

16:31 <bb-m-labs> build #2460 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2460

16:34 <bb-m-labs> build #2936 of artiq is complete: Failure [failed anaconda_upload_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2936 blamelist: Robert J?rdens <rj@quartiq.de>

16:36 <_whitenotifier-9> [nmigen] sam-falvo synchronize pull request #22: Updated user guide introduction for nmigen. - https://git.io/fhszI

16:36 <_whitenotifier-9> [nmigen] Failure. 85.51% (-0.02%) compared to 8ee6bd8 - https://codecov.io/gh/m-labs/nmigen/compare/8ee6bd80ff4fd0c2f5a42cde2c7c41b5fd919c9f...d4635a000ebb549e77246413baa0de0667c5ba7a

16:36 <_whitenotifier-9> [nmigen] Success. Coverage not affected when comparing 8ee6bd8...d4635a0 - https://codecov.io/gh/m-labs/nmigen/compare/8ee6bd80ff4fd0c2f5a42cde2c7c41b5fd919c9f...d4635a000ebb549e77246413baa0de0667c5ba7a

16:39 <kc5tja> Just a reminder, if anyone can take a peak at the documentation that I've produced thus far and provide a review before I move on to other things, that would be a great help to me. Thank you!

16:40 <kc5tja> (Also, would love feedback on what to document next. In the absence of any such feedback, I'll try to modernize a tutorial I have bookmarked for this purpose and include it as a chapter in the documentation.)

16:41 <kc5tja> attn whitequark ^

16:44 <_whitenotifier-9> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/496593101?utm_source=github_status&utm_medium=notification

16:44 <_whitenotifier-9> [nmigen] Success. 85.52% remains the same compared to 8ee6bd8 - https://codecov.io/gh/m-labs/nmigen/compare/8ee6bd80ff4fd0c2f5a42cde2c7c41b5fd919c9f...43808f768337d45982acd4a8dbfac91f94f58aee

16:44 <_whitenotifier-9> [nmigen] Success. Coverage not affected when comparing 8ee6bd8...43808f7 - https://codecov.io/gh/m-labs/nmigen/compare/8ee6bd80ff4fd0c2f5a42cde2c7c41b5fd919c9f...43808f768337d45982acd4a8dbfac91f94f58aee

16:45 <_whitenotifier-9> [nmigen] peteut commented on pull request #22: Updated user guide introduction for nmigen. - https://git.io/fhFRK

16:53 <_whitenotifier-9> [nmigen] peteut opened pull request #36: setup.py: constrain Python version - https://git.io/fhFR5

17:03 <_whitenotifier-9> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/496601924?utm_source=github_status&utm_medium=notification

17:03 <_whitenotifier-9> [nmigen] codecov[bot] commented on pull request #36: setup.py: constrain Python version - https://git.io/fhF0L

17:03 <_whitenotifier-9> [nmigen] Success. 85.52% remains the same compared to 8ee6bd8 - https://codecov.io/gh/m-labs/nmigen/compare/8ee6bd80ff4fd0c2f5a42cde2c7c41b5fd919c9f...81ab1fc9e816e99ecfafdd048990972438884284

17:03 <_whitenotifier-9> [nmigen] Success. Coverage not affected when comparing 8ee6bd8...81ab1fc - https://codecov.io/gh/m-labs/nmigen/compare/8ee6bd80ff4fd0c2f5a42cde2c7c41b5fd919c9f...81ab1fc9e816e99ecfafdd048990972438884284

17:07 <_whitenotifier-9> [nmigen] sam-falvo commented on pull request #22: Updated user guide introduction for nmigen. - https://git.io/fhF0m

17:22 <_whitenotifier-9> [nmigen] peteut commented on pull request #22: Updated user guide introduction for nmigen. - https://git.io/fhF0K