<_whitenotifier-9>
[nmigen] sbourdeauducq commented on issue #30: Module.prepare/rtlil.convert should not propagate inputs to toplevel unless explicitly requested - https://git.io/fh7lZ
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<lkcl>
hm, can someone help check if this is correct translation of verilog code to nmigen?
<lkcl>
with m.If(((a_e == 128) & (a_m != 0)) | \
<lkcl>
((b_e == 128) & (b_m != 0))):
<lkcl>
the original verilog is:
<lkcl>
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
<lkcl>
the output, which goes through a *lot* of $51s etc.. :)
<lkcl>
has the & operator not the && operator
<lkcl>
if i try to use "a_e == 128 and a_m != 0" nmigen says "cannot convert bool"
<lkcl>
suggestions welcome
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<attie>
lkcl: migen only has &, I assume nmigen is the same. the result of the equality/inequality is 1 bit anyway so it does the same.
<lkcl>
attie: ok whew :)
<attie>
I always thought of && as more of a system verilog thing, do you use it a lot?
<lkcl>
attie: well, i'm actually hopelessly clueless about verilog, i am used to gate-level design
<lkcl>
we're a team working on a libre 3D CPU/GPU SoC, and picked migen because we're mostly software engineering background
<lkcl>
currently experimenting by converting jondawson's IEEE754 FPU adder (verilog) to nmigen
<attie>
ah, right. kinda same, I only wrote a few dozen lines of verilog before switching to migen forever
<lkcl>
ah cool let me post that to the list as well
<attie>
it's actually not that complicated... until you get into the corner cases
<attie>
this one does not handle all of the corner cases according to spec iirc
<lkcl>
yehyeh i could sort-of tell (from the length)
<attie>
like denormalization, NaN, positive/negative infinity
<lkcl>
yehyeh, jon added all that stuff. i just did the special-cases block
<lkcl>
i have a vague idea of what the denormalised numbers are.
<attie>
I actually wonder how that interacts with the DSP block inference.
<attie>
do the DSP blocks handle the corner cases?
<lkcl>
very unlikely.
<lkcl>
it's likely that the DSP part is just the integer-add / integer-mult
<lkcl>
integer-mult in an FPGA as LUTs (etc.) would be enormous
<attie>
yeah
<attie>
I had to implement a division for this project
<lkcl>
i'm going to suggest to the team that we add in some functions to the class, which create numbers from sign/exp/mant
<lkcl>
oh really!
<attie>
luckily I only needed to divide by an integer so I was able to simplify it
<attie>
it still takes 50 cycles
<lkcl>
oo, oo, did you know that sqrt can be done as a pipeline by "long sqrt" just like "long division"?
<attie>
and it gives the wrong result I believe, but I never cared because I only need it as a benchmark for how fast it goes
<lkcl>
eek that's a lot
<lkcl>
:)
<lkcl>
you know how (a^2 + b^2) can be rewritten as a^2 + b(2a + b) ?
<lkcl>
long-square-root works by moving bits from a to b
<lkcl>
and if it's done in binary, one bit at a time, you only need an adder and a comparator to do square-root!
<lkcl>
i learned long-square-root when i was... err... 14 i think :)
<attie>
that sounds cool but I'm not getting it ^^"
<lkcl>
:)
<lkcl>
well, if ever you need it, you'll know where to look, as we have to implement it for the soc
<attie>
that's the most important bit :D
<lkcl>
alright managed to reach a milestone, off for a coffee, back later
<lkcl>
thanks for clarifying on & and &&.
<attie>
np!
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<keesj>
anybody from lambdaconcept here?
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<lkcl>
whitequark, sb0: ping, negative slice indices don't seem to be supported in nmigen
<whitequark>
lkcl: pong
<whitequark>
file an issue and i'll fix it
<_whitenotifier-9>
[nmigen] whitequark commented on issue #30: Module.prepare/rtlil.convert should not propagate inputs to toplevel unless explicitly requested - https://git.io/fh7zU
<lkcl>
whitequark: hdl/ast.py line 402 it *should* be working
<lkcl>
line 112, key = len(self)... should return the right number... hmmm...
<lkcl>
whitequark, ep, think i got it. my bug
<lkcl>
hmmm... is there anything in nmigen that could be used as a CAM?
<lkcl>
as the basis for a CAM, sorry
<lkcl>
whitequark: is that basically SignalDict?
<whitequark>
no, SignalDict is an internal thing
<whitequark>
what would a CAM synthesize to?
<lkcl>
it's basically a key-value store, so there would be an array of comparator signals for the "keys"
<lkcl>
hmm... what happens to the values is likely to be application-specific.
<lkcl>
some applications (such as a TLB for virtual memory), it would be a severe (hard) error if the keys were not unique
<lkcl>
so it would be a *type* of (multi-ported) Memory
<lkcl>
some applications would actually want logic to be activated (in parallel) on each and every "value" if the "key" matches
<lkcl>
hmmm... need to think about that one :)
<lkcl>
we're doing a TLB in nmigen, btw.
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<keesj>
and the sync block first does self.seconds.eq(self.seconds + 1)
<keesj>
is self.second (line 6) then already seconds +1?
<keesj>
e.g. I see the <= operator being used and my understanding was that the value will only be true after the always block is done
<keesj>
"<=" in Verilog is called non-blocking assignment which brings a whole lot of difference than "=" which is called as blocking assignment because of scheduling events in any vendor based simulators.
<whitequark>
the assignment is non-blocking when used in self.sync, yes
<keesj>
it does add the functionality to increase minutes and seconds but does this in an if/elif/else statement
<keesj>
it looks like a possible overflow but if indeed the assiment is non-blocking (I just verified this) it would not be possible to increase the minute to over 60
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<_whitenotifier-9>
[m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fh7M7
<_whitenotifier-9>
[m-labs/nmigen] whitequark 8ee6bd8 - hdl.ir: raise a more descriptive error on non-elaboratable object.
<_whitenotifier-9>
[nmigen] whitequark commented on pull request #33: Give hint when user forgets to return `Module` from `elaborate`. - https://git.io/fh7M5
<_whitenotifier-9>
[nmigen] whitequark closed pull request #33: Give hint when user forgets to return `Module` from `elaborate`. - https://git.io/fhXVp